From: Jacob Lifshay <programmerjake@gmail.com>
Date: Thu, 6 Jan 2022 04:32:22 +0000 (-0800)
Subject: add todos
X-Git-Tag: opf_rfc_ls005_v1~3269
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=d1005d9e3618ae2c211ae2e8758a5026f90d9a0d;p=libreriscv.git

add todos
---

diff --git a/openpower/sv/bitmanip.mdwn b/openpower/sv/bitmanip.mdwn
index cc91c1e42..dfa34536b 100644
--- a/openpower/sv/bitmanip.mdwn
+++ b/openpower/sv/bitmanip.mdwn
@@ -73,6 +73,8 @@ minor opcode allocation
 * ternlog bitops
 * GF
 
+TODO: convert all instructions to use RT and not RS
+
 | 0.5|6.10|11.15|16.20|21..25 | 26....30 |31| name |
 | -- | -- | --- | --- | ----- | -------- |--| ------ |
 | NN | RT | RA  | RB  | RC    | mode 000 |1 | ternlog |
@@ -94,6 +96,9 @@ minor opcode allocation
 ops (note that av avg and abs as well as vec scalar mask
 are included here)
 
+TODO: convert from RA, RB, and RC to correct field names of RT, RA, and RB, and
+double check that instructions didn't need 3 inputs.
+
 | 0.5|6.10|11.15|16.20| 21 | 22.23 | 24....30 |31| name |
 | -- | -- | --- | --- | -- | ----- | -------- |--| ---- |
 | NN | RA | RB  |     | 0  |       | 0000 110 |Rc| rsvd   |