From: Clifford Wolf Date: Wed, 3 Jul 2019 08:45:29 +0000 (+0200) Subject: Merge pull request #1154 from whitequark/manual-sync-always X-Git-Tag: yosys-0.9~23 X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=d105e2f03f259e4f2be3d6d9ba970565d8422b87;p=yosys.git Merge pull request #1154 from whitequark/manual-sync-always manual: explain the purpose of `sync always` --- diff --git a/manual/CHAPTER_Overview.tex b/manual/CHAPTER_Overview.tex index 1a25c477f..3009bf2c0 100644 --- a/manual/CHAPTER_Overview.tex +++ b/manual/CHAPTER_Overview.tex @@ -331,8 +331,9 @@ to update {\tt \textbackslash{}q}. An RTLIL::Process is a container for zero or more RTLIL::SyncRule objects and exactly one RTLIL::CaseRule object, which is called the {\it root case}. -An RTLIL::SyncRule object contains an (optional) synchronization condition -(signal and edge-type) and zero or more assignments (RTLIL::SigSig). +An RTLIL::SyncRule object contains an (optional) synchronization condition (signal and edge-type) and zero or +more assignments (RTLIL::SigSig). The {\tt always} synchronization condition is used to break combinatorial +loops when a latch should be inferred instead. An RTLIL::CaseRule is a container for zero or more assignments (RTLIL::SigSig) and zero or more RTLIL::SwitchRule objects. An RTLIL::SwitchRule objects is a