From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Sat, 21 Mar 2020 11:48:14 +0000 (+0000)
Subject: shorten variables, add comments
X-Git-Tag: div_pipeline~1661
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=d1188ddc234ce876cbffd6ad823924e1643998ce;p=soc.git

shorten variables, add comments
---

diff --git a/src/soc/decoder/test/test_decoder_gas.py b/src/soc/decoder/test/test_decoder_gas.py
index 52ae7977..6485cbcf 100644
--- a/src/soc/decoder/test/test_decoder_gas.py
+++ b/src/soc/decoder/test/test_decoder_gas.py
@@ -419,17 +419,17 @@ class DecoderTestCase(FHDLTestCase):
         def process():
             for i in range(20):
                 checker = kls()
-                instruction_str = checker.generate_instruction()
-                print("instr", instruction_str.strip())
-                for endian in [0, 1]:
+                ins = checker.generate_instruction()
+                print("instr", ins.strip())
+                for mode in [0, 1]:
 
-                    instruction_bin = self.get_assembled_instruction(
-                        instruction_str, endian)
-                    print("code", endian, hex(instruction_bin),
-                                          bin(instruction_bin))
+                    # turn the instruction into binary data (endian'd)
+                    ibin = self.get_assembled_instruction(ins, mode)
+                    print("code", mode, hex(ibin), bin(ibin))
 
-                    yield pdecode2.dec.bigendian.eq(endian)
-                    yield instruction.eq(instruction_bin)
+                    # ask the decoder to decode this binary data (endian'd)
+                    yield pdecode2.dec.bigendian.eq(endian) # little / big?
+                    yield instruction.eq(ibin)              # raw binary instr.
                     yield Delay(1e-6)
 
                     yield from checker.check_results(pdecode2)