From: Giacomo Travaglini <giacomo.travaglini@arm.com>
Date: Fri, 30 Aug 2019 13:31:57 +0000 (+0100)
Subject: arch-arm: SySDC64 Instructions (CMO) using MiscRegIndex
X-Git-Tag: v19.0.0.0~579
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=d1251cd2c64a6bdbca38b65a7a9dc533c54f7f5c;p=gem5.git

arch-arm: SySDC64 Instructions (CMO) using MiscRegIndex

Change-Id: Ia66d6abf965b1d33579e8fa048608d99c93ff2ce
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20621
Tested-by: kokoro <noreply+kokoro@google.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
---

diff --git a/src/arch/arm/insts/mem64.hh b/src/arch/arm/insts/mem64.hh
index 4fbbe7791..886c54f35 100644
--- a/src/arch/arm/insts/mem64.hh
+++ b/src/arch/arm/insts/mem64.hh
@@ -49,13 +49,13 @@ class SysDC64 : public MiscRegOp64
 {
   protected:
     IntRegIndex base;
-    IntRegIndex dest;
+    MiscRegIndex dest;
     uint64_t imm;
 
     SysDC64(const char *mnem, ExtMachInst _machInst, OpClass __opClass,
-            IntRegIndex _base, MiscRegIndex miscReg, uint64_t _imm)
+            IntRegIndex _base, MiscRegIndex _dest, uint64_t _imm)
         : MiscRegOp64(mnem, _machInst, __opClass, false),
-          base(_base), dest((IntRegIndex)miscReg), imm(_imm)
+          base(_base), dest(_dest), imm(_imm)
     {}
 
     std::string generateDisassembly(