From: Vladimir Makarov <vmakarov@redhat.com>
Date: Fri, 8 Jul 2016 20:29:12 +0000 (+0000)
Subject: re PR rtl-optimization/71621 (ICE in assign_by_spills, at lra-assigns.c:1417 (error... 
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=d13835b668ac64ae062fa0c765476d229b6b2c22;p=gcc.git

re PR rtl-optimization/71621 (ICE in assign_by_spills, at lra-assigns.c:1417 (error: unable to find a register to spill) w/ -O2 -mavx2 -ftree-vectorize)

2016-07-08  Vladimir Makarov  <vmakarov@redhat.com>

	PR rtl-optimization/71621
	* lra-constraints.c (process_alt_operands): Check combination of
	reg class and mode.

2016-07-08  Vladimir Makarov  <vmakarov@redhat.com>

	PR rtl-optimization/71621
	* gcc.target/i386/pr71621-1.c: New.
	* gcc.target/i386/pr71621-2.c: New.

From-SVN: r238178
---

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index 105d110a55f..9cdfd1a86e9 100644
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,9 @@
+2016-07-08  Vladimir Makarov  <vmakarov@redhat.com>
+
+	PR rtl-optimization/71621
+	* lra-constraints.c (process_alt_operands): Check combination of
+	reg class and mode.
+
 2016-06-25  Jason Merrill  <jason@redhat.com>
 	    Richard Biener  <rguenther@suse.de>
 
diff --git a/gcc/lra-constraints.c b/gcc/lra-constraints.c
index e9d3e43eace..a1119ac70fd 100644
--- a/gcc/lra-constraints.c
+++ b/gcc/lra-constraints.c
@@ -2261,6 +2261,41 @@ process_alt_operands (int only_alternative)
 		  goto fail;
 		}
 
+	      if (this_alternative != NO_REGS)
+		{
+		  HARD_REG_SET available_regs;
+		  
+		  COPY_HARD_REG_SET (available_regs,
+				     reg_class_contents[this_alternative]);
+		  AND_COMPL_HARD_REG_SET
+		    (available_regs,
+		     ira_prohibited_class_mode_regs[this_alternative][mode]);
+		  AND_COMPL_HARD_REG_SET (available_regs, lra_no_alloc_regs);
+		  if (hard_reg_set_empty_p (available_regs))
+		    {
+		      /* There are no hard regs holding a value of given
+			 mode.  */
+		      if (offmemok)
+			{
+			  this_alternative = NO_REGS;
+			  if (lra_dump_file != NULL)
+			    fprintf (lra_dump_file,
+				     "            %d Using memory because of"
+				     " a bad mode: reject+=2\n",
+				     nop);
+			  reject += 2;
+			}
+		      else
+			{
+			  if (lra_dump_file != NULL)
+			    fprintf (lra_dump_file,
+				     "            alt=%d: Wrong mode -- refuse\n",
+				     nalt);
+			  goto fail;
+			}
+		    }
+		}
+
 	      /* If not assigned pseudo has a class which a subset of
 		 required reg class, it is a less costly alternative
 		 as the pseudo still can get a hard reg of necessary
diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog
index 5245fdd44df..1d835813da8 100644
--- a/gcc/testsuite/ChangeLog
+++ b/gcc/testsuite/ChangeLog
@@ -1,3 +1,9 @@
+2016-07-08  Vladimir Makarov  <vmakarov@redhat.com>
+
+	PR rtl-optimization/71621
+	* gcc.target/i386/pr71621-1.c: New.
+	* gcc.target/i386/pr71621-2.c: New.
+
 2016-07-08  Cesar Philippidis  <cesar@codesourcery.com>
 
 	* gfortran.dg/goacc/pr71704.f90: New test.
diff --git a/gcc/testsuite/gcc.target/i386/pr71621-1.c b/gcc/testsuite/gcc.target/i386/pr71621-1.c
new file mode 100644
index 00000000000..43df5a8f0ae
--- /dev/null
+++ b/gcc/testsuite/gcc.target/i386/pr71621-1.c
@@ -0,0 +1,31 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -w -ftree-vectorize -mavx2" } */
+
+int cn;
+int *li;
+
+void
+y8 (void)
+{
+  int gv;
+  int *be = &gv;
+  short int v4 = 2;
+
+  while (*li != 0)
+    {
+      int sy;
+      for (sy = 0; sy < 5; ++sy)
+	{
+	  int **t6 = &be;
+	  gv |= sy ? 0 : v4;
+	  if (gv != 0)
+	    ++gv;
+	  t6 = &cn;
+	  if (gv != 0)
+	    *t6 = 0;
+	}
+      for (gv = 0; gv < 24; ++gv)
+	v4 |= 1 <= 1 % 0;
+      ++(*li);
+    }
+}
diff --git a/gcc/testsuite/gcc.target/i386/pr71621-2.c b/gcc/testsuite/gcc.target/i386/pr71621-2.c
new file mode 100644
index 00000000000..175b7d2f931
--- /dev/null
+++ b/gcc/testsuite/gcc.target/i386/pr71621-2.c
@@ -0,0 +1,39 @@
+/* { dg-do compile } */
+/* { dg-options "-O3 -mavx2" } */
+
+int hf, sv, zz, aj;
+
+void
+dn (int xb, int bl)
+{
+  while (zz < 1)
+    {
+      if (xb == 0)
+	goto mr;
+
+      while (bl < 3)
+	{
+	  int d3;
+	  unsigned char vh;
+	  unsigned char *fj = &vh;
+
+	mr:
+	  while (bl < 1)
+	    {
+	      hf += vh;
+	      ++bl;
+	    }
+	  if (xb == 0)
+	    zz = bl;
+	  if (d3 == 0)
+	    return;
+	  while (sv < 1)
+	    {
+	      --vh;
+	      aj += vh;
+	      ++sv;
+	    }
+	}
+      sv = 0;
+    }
+}