From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Wed, 15 Jul 2020 15:11:19 +0000 (+0100)
Subject: add better comments on mul overflow
X-Git-Tag: div_pipeline~17
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=d139c34e6c337d692341609236c1d00579a33df5;p=soc.git

add better comments on mul overflow
---

diff --git a/src/soc/config/endian.py b/src/soc/config/endian.py
index 0aaa61c2..eb6e0c3f 100644
--- a/src/soc/config/endian.py
+++ b/src/soc/config/endian.py
@@ -1,5 +1,5 @@
 global bigendian
-bigendian = 1
+bigendian = 0
 
 def set_endian_mode(mode):
     bigendian = mode
diff --git a/src/soc/fu/mul/post_stage.py b/src/soc/fu/mul/post_stage.py
index 1c144ad1..dbe560e9 100644
--- a/src/soc/fu/mul/post_stage.py
+++ b/src/soc/fu/mul/post_stage.py
@@ -54,14 +54,18 @@ class MulMainStage3(PipeModBase):
                 # take the low 64 bits of the mul
                 comb += o.data.eq(mul_o[0:64])
 
-                # compute overflow
+                # compute overflow 32/64
                 mul_ov = Signal(reset_less=True)
                 with m.If(is_32bit):
-                    m32 = mul_o[31:64] # yes really bits 31 to 63 (incl)
-                    comb += mul_ov.eq(m32.bool() & ~m32.all())
+                    # here we're checking that the top 32 bits is the
+                    # sign-extended version of the bottom 32 bits.
+                    m31 = mul_o[31:64] # yes really bits 31 to 63 (incl)
+                    comb += mul_ov.eq(m31.bool() & ~m31.all())
                 with m.Else():
-                    m64 = mul_o[63:128] # yes really bits 63 to 127 (incl)
-                    comb += mul_ov.eq(m64.bool() & ~m64.all())
+                    # here we're checking that the top 64 bits is the
+                    # sign-extended version of the bottom 64 bits.
+                    m63 = mul_o[63:128] # yes really bits 63 to 127 (incl)
+                    comb += mul_ov.eq(m63.bool() & ~m63.all())
 
                 # 32-bit (ov[1]) and 64-bit (ov[0]) overflow - both same
                 comb += ov_o.data.eq(Repl(mul_ov, 2)) # sets OV _and_ OV32