From: Tim 'mithro' Ansell <me@mith.ro>
Date: Thu, 4 Oct 2018 04:57:24 +0000 (-0700)
Subject: cpu/mor1kx: Adding verilog include directory.
X-Git-Tag: 24jan2021_ls180~1555^2~3
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=d13ac3b3d504224aa2449612ad181c27b8ab0ba4;p=litex.git

cpu/mor1kx: Adding verilog include directory.
---

diff --git a/litex/soc/cores/cpu/mor1kx/core.py b/litex/soc/cores/cpu/mor1kx/core.py
index 7428211e..c53c6e5e 100644
--- a/litex/soc/cores/cpu/mor1kx/core.py
+++ b/litex/soc/cores/cpu/mor1kx/core.py
@@ -122,3 +122,4 @@ class MOR1KX(Module):
             os.path.abspath(os.path.dirname(__file__)),
             "verilog", "rtl", "verilog")
         platform.add_source_dir(vdir)
+        platform.add_verilog_include_path(vdir)