From: lkcl <lkcl@web>
Date: Wed, 21 Sep 2022 12:46:40 +0000 (+0100)
Subject: (no commit message)
X-Git-Tag: opf_rfc_ls005_v1~346
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=d1421e8722a1950021a654c181bac6a0c7634633;p=libreriscv.git

---

diff --git a/openpower/sv.mdwn b/openpower/sv.mdwn
index 6dd587c01..680760a45 100644
--- a/openpower/sv.mdwn
+++ b/openpower/sv.mdwn
@@ -253,6 +253,30 @@ Load-with-Update).
 Explanation of the rules for twin register targets
 (implicit RS, FRS) explained in SVP64 [[svp64/appendix]]
 
+# Architectural Note
+
+This section is primarily for the ISA Working Group and for IBM
+in their capacity and responsibility for allocating "Architectural
+Resources" (opcodes), but it is also useful for general understanding
+of Simple-V.
+
+Simple-V is effectively a type of "Zero-Overhead Loop Control" to which
+an entire 24 bits are exclusively dedicated in a fully RISC-abstracted
+manner.  This is why there are no Vector operations: *all* suitable
+Scalar Operations are Vectorised or not at all.  This has some extremely
+important implications when considering adding new instructions, and
+especially when allocating the Opcode Space for them.
+To protect SVP64 from damage, a "Hard Rule" has to be set:
+
+     Scalar Instructions must be simultaneously added in the corresponding
+     SVP64 opcode space with the exact same 32-bit "Defined Word" or they
+     must not be added at all.  Likewise instructions planned for addition
+     in what is considered (wrongly) to be the exclusive "Vector" domain
+     must correspondingly be added in the Scalar space with the exact same
+     32-bit "Defined Word" or not at all.
+
+
+
 # Other Scalable Vector ISAs
 
 These Scalable Vector ISAs are listed to aid in understanding and