From: Clifford Wolf <clifford@clifford.at>
Date: Wed, 27 Aug 2014 17:44:12 +0000 (+0200)
Subject: Fixed inserting of Q-inverters in dfflibmap
X-Git-Tag: yosys-0.4~202
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=d148b0af0d5d1a039b13b9e610859a2e55da945e;p=yosys.git

Fixed inserting of Q-inverters in dfflibmap
---

diff --git a/passes/techmap/dfflibmap.cc b/passes/techmap/dfflibmap.cc
index 7e39040c4..07993b868 100644
--- a/passes/techmap/dfflibmap.cc
+++ b/passes/techmap/dfflibmap.cc
@@ -409,6 +409,11 @@ static void dfflibmap(RTLIL::Design *design, RTLIL::Module *module)
 			if ('A' <= port.second && port.second <= 'Z') {
 				sig = cell_connections[std::string("\\") + port.second];
 			} else
+			if (port.second == 'q') {
+				RTLIL::SigSpec old_sig = cell_connections[std::string("\\") + char(port.second - ('a' - 'A'))];
+				sig = module->addWire(NEW_ID, SIZE(old_sig));
+				module->addNotGate(NEW_ID, sig, old_sig);
+			} else
 			if ('a' <= port.second && port.second <= 'z') {
 				sig = cell_connections[std::string("\\") + char(port.second - ('a' - 'A'))];
 				sig = module->NotGate(NEW_ID, sig);