From: Robin Ole Heinemann <robin.ole.heinemann@gmail.com>
Date: Sat, 2 Jan 2021 23:13:46 +0000 (+0100)
Subject: lib.fifo: use proper clock domains in AsyncFIFO tests
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=d15705cf4f32586facfa7431bf54f30f88eaf4d0;p=nmigen.git

lib.fifo: use proper clock domains in AsyncFIFO tests
---

diff --git a/tests/test_lib_fifo.py b/tests/test_lib_fifo.py
index bd5a9d9..d276b3d 100644
--- a/tests/test_lib_fifo.py
+++ b/tests/test_lib_fifo.py
@@ -312,16 +312,16 @@ class AsyncFIFOSimCase(FHDLTestCase):
             for i in range(fill_in):
                 yield fifo.w_data.eq(i)
                 yield fifo.w_en.eq(1)
-                yield
+                yield Tick("write")
             yield fifo.w_en.eq(0)
-            yield
-            yield
+            yield Tick("write")
+            yield Tick("write")
             self.assertEqual((yield fifo.w_level), expected_level)
             yield write_done.eq(1)
 
         def read_process():
             while not (yield write_done):
-                yield
+                yield Tick("read")
             self.assertEqual((yield fifo.r_level), expected_level)
 
         simulator = Simulator(fifo)