From: Clifford Wolf <clifford@clifford.at>
Date: Thu, 9 Apr 2015 13:12:26 +0000 (+0200)
Subject: Minor fixes in handling of "init" attribute
X-Git-Tag: yosys-0.6~338
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=d176e613c2fea8d5ac5d9bf505b188ca13da95ef;p=yosys.git

Minor fixes in handling of "init" attribute
---

diff --git a/backends/verilog/verilog_backend.cc b/backends/verilog/verilog_backend.cc
index 0d667c638..c6d595c38 100644
--- a/backends/verilog/verilog_backend.cc
+++ b/backends/verilog/verilog_backend.cc
@@ -295,15 +295,15 @@ void dump_wire(std::ostream &f, std::string indent, RTLIL::Wire *wire)
 		f << stringf("%s" "output%s %s;\n", indent.c_str(), range.c_str(), id(wire->name).c_str());
 	if (wire->port_input && wire->port_output)
 		f << stringf("%s" "inout%s %s;\n", indent.c_str(), range.c_str(), id(wire->name).c_str());
-	if (reg_wires.count(wire->name))
+	if (reg_wires.count(wire->name)) {
 		f << stringf("%s" "reg%s %s;\n", indent.c_str(), range.c_str(), id(wire->name).c_str());
-	else if (!wire->port_input && !wire->port_output)
+		if (wire->attributes.count("\\init")) {
+			f << stringf("%s" "initial %s = ", indent.c_str(), id(wire->name).c_str());
+			dump_const(f, wire->attributes.at("\\init"));
+			f << stringf(";\n");
+		}
+	} else if (!wire->port_input && !wire->port_output)
 		f << stringf("%s" "wire%s %s;\n", indent.c_str(), range.c_str(), id(wire->name).c_str());
-	if (wire->attributes.count("\\init")) {
-		f << stringf("%s" "initial %s = ", indent.c_str(), id(wire->name).c_str());
-		dump_const(f, wire->attributes.at("\\init"));
-		f << stringf(";\n");
-	}
 #endif
 }
 
diff --git a/passes/proc/proc_arst.cc b/passes/proc/proc_arst.cc
index 27c6b3bcf..1f08ab042 100644
--- a/passes/proc/proc_arst.cc
+++ b/passes/proc/proc_arst.cc
@@ -244,6 +244,7 @@ struct ProcArstPass : public Pass {
 		}
 
 		extra_args(args, argidx, design);
+		pool<Wire*> delete_initattr_wires;
 
 		for (auto mod : design->modules())
 			if (design->selected(mod)) {
@@ -265,6 +266,7 @@ struct ProcArstPass : public Pass {
 										value.extend_u0(chunk.wire->width, false);
 										arst_sig.append(chunk);
 										arst_val.append(value.extract(chunk.offset, chunk.width));
+										delete_initattr_wires.insert(chunk.wire);
 									}
 								if (arst_sig.size()) {
 									log("Added global reset to process %s: %s <- %s\n",
@@ -281,6 +283,9 @@ struct ProcArstPass : public Pass {
 					}
 				}
 			}
+
+		for (auto wire : delete_initattr_wires)
+			wire->attributes.erase("\\init");
 	}
 } ProcArstPass;