From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Sat, 17 Aug 2019 08:13:28 +0000 (+0100)
Subject: assignment in Cat wrong way round
X-Git-Tag: ls180-24jan2020~513
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=d17d98296f54c5851e81e5e96c0322ed5b99c167;p=ieee754fpu.git

assignment in Cat wrong way round
---

diff --git a/src/ieee754/part_mul_add/multiply.py b/src/ieee754/part_mul_add/multiply.py
index 3b604bda..ee28d403 100644
--- a/src/ieee754/part_mul_add/multiply.py
+++ b/src/ieee754/part_mul_add/multiply.py
@@ -199,7 +199,7 @@ class PartitionedAdder(Elaboratable):
         # combine above using Cat
         m.d.comb += Cat(*ea).eq(Cat(*al))
         m.d.comb += Cat(*eb).eq(Cat(*bl))
-        m.d.comb += Cat(*eo).eq(Cat(*ol))
+        m.d.comb += Cat(*ol).eq(Cat(*eo))
         # use only one addition to take advantage of look-ahead carry and
         # special hardware on FPGAs
         m.d.comb += self._expanded_output.eq(