From: whitequark <cz@m-labs.hk>
Date: Fri, 21 Dec 2018 10:25:28 +0000 (+0000)
Subject: back.pysim: fix an issue with too few funclet slots.
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=d17ee3decbcda4e0a1b5fe326eb275183b75de8c;p=nmigen.git

back.pysim: fix an issue with too few funclet slots.
---

diff --git a/nmigen/back/pysim.py b/nmigen/back/pysim.py
index 7baa654..2d86d0a 100644
--- a/nmigen/back/pysim.py
+++ b/nmigen/back/pysim.py
@@ -437,6 +437,8 @@ class Simulator:
                         self._domain_signals[domain] = bitarray()
                     self._domain_signals[domain].append(False)
 
+                self._funclets.append(set())
+
                 self._domain_triggers.append(None)
                 if self._vcd_writer:
                     self._vcd_signals.append(set())
@@ -520,10 +522,7 @@ class Simulator:
             funclet = compiler(statements)
 
             def add_funclet(signal, funclet):
-                signal_slot = self._signal_slots[signal]
-                while len(self._funclets) <= signal_slot:
-                    self._funclets.append(set())
-                self._funclets[signal_slot].add(funclet)
+                self._funclets[self._signal_slots[signal]].add(funclet)
 
             for signal in compiler.sensitivity:
                 add_funclet(signal, funclet)