From: Daniel Benusovich <flyingmonkeys1996@gmail.com>
Date: Sat, 23 Feb 2019 18:41:00 +0000 (-0800)
Subject: Moving test_cam_entry
X-Git-Tag: div_pipeline~2378
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=d17f7583ed4004fdee004b1bec83f451b81d2c1d;p=soc.git

Moving test_cam_entry
---

diff --git a/TLB/test/test_cam_entry.py b/TLB/test/test_cam_entry.py
new file mode 100644
index 00000000..07c09c48
--- /dev/null
+++ b/TLB/test/test_cam_entry.py
@@ -0,0 +1,122 @@
+import sys
+sys.path.append("../src")
+sys.path.append("../../TestUtil")
+
+from nmigen.compat.sim import run_simulation
+
+from test_helper import check
+from CamEntry import CamEntry
+ 
+# This function allows for the easy setting of values to the Cam Entry
+# unless the key is incorrect
+# Arguments:
+#   dut: The CamEntry being tested
+#   c (command): NA (0), Read (1), Write (2), Reserve (3)
+#   k (key): The key to be set
+#   d (data): The data to be set  
+def set_cam_entry(dut, c, k, d):
+    # Write desired values
+    yield dut.command.eq(c)
+    yield dut.key_in.eq(k)
+    yield dut.data_in.eq(d)
+    yield
+    # Reset all lines
+    yield dut.command.eq(0)
+    yield dut.key_in.eq(0)
+    yield dut.data_in.eq(0)    
+    yield    
+
+# Checks the key state of the CAM entry
+# Arguments:
+#   dut: The CamEntry being tested
+#   k (Key): The expected key
+#   op (Operation): (0 => ==), (1 => !=)
+def check_key(dut, k, op):
+    out_k = yield dut.key
+    check("Key", out_k, k, op)   
+   
+# Checks the data state of the CAM entry
+# Arguments:
+#   dut: The CamEntry being tested
+#   d (Data): The expected data
+#   op (Operation): (0 => ==), (1 => !=)
+def check_data(dut, d, op):
+    out_d = yield dut.data
+    check("Data", out_d, d, op)   
+  
+# Checks the match state of the CAM entry
+# Arguments:
+#   dut: The CamEntry being tested
+#   m (Match): The expected match  
+#   op (Operation): (0 => ==), (1 => !=)
+def check_match(dut, m, op):
+    out_m = yield dut.match
+    check("Match", out_m, m, op)  
+  
+# Checks the state of the CAM entry
+# Arguments:
+#   dut: The CamEntry being tested
+#   k (key): The expected key  
+#   d (data): The expected data
+#   m (match): The expected match  
+#   k_op (Operation): The operation for the key assertion (0 => ==), (1 => !=)
+#   d_op (Operation): The operation for the data assertion (0 => ==), (1 => !=)
+#   m_op (Operation): The operation for the match assertion (0 => ==), (1 => !=)
+def check_all(dut, k, d, m, k_op, d_op, m_op):
+    yield from check_key(dut, k, k_op)
+    yield from check_data(dut, d, d_op)
+    yield from check_match(dut, m, m_op)
+    
+# This testbench goes through the paces of testing the CamEntry module
+# It is done by writing and then reading various combinations of key/data pairs
+# and reading the results with varying keys to verify the resulting stored
+# data is correct.
+def testbench(dut):
+    # Check write
+    command = 2
+    key = 1
+    data = 1
+    match = 0
+    yield from set_cam_entry(dut, command, key, data)
+    yield from check_all(dut, key, data, match, 0, 0, 0)
+    
+    # Check read miss
+    command = 1
+    key = 2
+    data = 1
+    match = 0 
+    yield from set_cam_entry(dut, command, key, data)
+    yield from check_all(dut, key, data, match, 1, 0, 0) 
+    
+    # Check read hit
+    command = 1
+    key = 1
+    data = 1
+    match = 1
+    yield from set_cam_entry(dut, command, key, data)
+    yield from check_all(dut, key, data, match, 0, 0, 0) 
+    
+    # Check overwrite
+    command = 2
+    key = 2
+    data = 5
+    match = 0
+    yield from set_cam_entry(dut, command, key, data)
+    yield
+    yield from check_all(dut, key, data, match, 0, 0, 0) 
+    
+    # Check read hit
+    command = 1
+    key = 2
+    data = 5
+    match = 1
+    yield from set_cam_entry(dut, command, key, data)
+    yield from check_all(dut, key, data, match, 0, 0, 0) 
+    
+    # Extra clock cycle for waveform
+    yield
+    
+if __name__ == "__main__":
+    dut = CamEntry(4, 4)
+    run_simulation(dut, testbench(dut), vcd_name="Waveforms/cam_entry_test.vcd")
+    print("CamEntry Unit Test Success")
diff --git a/TLB/test_cam_entry.py b/TLB/test_cam_entry.py
deleted file mode 100644
index 53240fcb..00000000
--- a/TLB/test_cam_entry.py
+++ /dev/null
@@ -1,118 +0,0 @@
-from nmigen.compat.sim import run_simulation
-
-from test_helper import check
-from CamEntry import CamEntry
- 
-# This function allows for the easy setting of values to the Cam Entry
-# unless the key is incorrect
-# Arguments:
-#   dut: The CamEntry being tested
-#   c (command): NA (0), Read (1), Write (2), Reserve (3)
-#   k (key): The key to be set
-#   d (data): The data to be set  
-def set_cam_entry(dut, c, k, d):
-    # Write desired values
-    yield dut.command.eq(c)
-    yield dut.key_in.eq(k)
-    yield dut.data_in.eq(d)
-    yield
-    # Reset all lines
-    yield dut.command.eq(0)
-    yield dut.key_in.eq(0)
-    yield dut.data_in.eq(0)    
-    yield    
-
-# Checks the key state of the CAM entry
-# Arguments:
-#   dut: The CamEntry being tested
-#   k (Key): The expected key
-#   op (Operation): (0 => ==), (1 => !=)
-def check_key(dut, k, op):
-    out_k = yield dut.key
-    check("Key", out_k, k, op)   
-   
-# Checks the data state of the CAM entry
-# Arguments:
-#   dut: The CamEntry being tested
-#   d (Data): The expected data
-#   op (Operation): (0 => ==), (1 => !=)
-def check_data(dut, d, op):
-    out_d = yield dut.data
-    check("Data", out_d, d, op)   
-  
-# Checks the match state of the CAM entry
-# Arguments:
-#   dut: The CamEntry being tested
-#   m (Match): The expected match  
-#   op (Operation): (0 => ==), (1 => !=)
-def check_match(dut, m, op):
-    out_m = yield dut.match
-    check("Match", out_m, m, op)  
-  
-# Checks the state of the CAM entry
-# Arguments:
-#   dut: The CamEntry being tested
-#   k (key): The expected key  
-#   d (data): The expected data
-#   m (match): The expected match  
-#   k_op (Operation): The operation for the key assertion (0 => ==), (1 => !=)
-#   d_op (Operation): The operation for the data assertion (0 => ==), (1 => !=)
-#   m_op (Operation): The operation for the match assertion (0 => ==), (1 => !=)
-def check_all(dut, k, d, m, k_op, d_op, m_op):
-    yield from check_key(dut, k, k_op)
-    yield from check_data(dut, d, d_op)
-    yield from check_match(dut, m, m_op)
-    
-# This testbench goes through the paces of testing the CamEntry module
-# It is done by writing and then reading various combinations of key/data pairs
-# and reading the results with varying keys to verify the resulting stored
-# data is correct.
-def testbench(dut):
-    # Check write
-    command = 2
-    key = 1
-    data = 1
-    match = 0
-    yield from set_cam_entry(dut, command, key, data)
-    yield from check_all(dut, key, data, match, 0, 0, 0)
-    
-    # Check read miss
-    command = 1
-    key = 2
-    data = 1
-    match = 0 
-    yield from set_cam_entry(dut, command, key, data)
-    yield from check_all(dut, key, data, match, 1, 0, 0) 
-    
-    # Check read hit
-    command = 1
-    key = 1
-    data = 1
-    match = 1
-    yield from set_cam_entry(dut, command, key, data)
-    yield from check_all(dut, key, data, match, 0, 0, 0) 
-    
-    # Check overwrite
-    command = 2
-    key = 2
-    data = 5
-    match = 0
-    yield from set_cam_entry(dut, command, key, data)
-    yield
-    yield from check_all(dut, key, data, match, 0, 0, 0) 
-    
-    # Check read hit
-    command = 1
-    key = 2
-    data = 5
-    match = 1
-    yield from set_cam_entry(dut, command, key, data)
-    yield from check_all(dut, key, data, match, 0, 0, 0) 
-    
-    # Extra clock cycle for waveform
-    yield
-    
-if __name__ == "__main__":
-    dut = CamEntry(4, 4)
-    run_simulation(dut, testbench(dut), vcd_name="Waveforms/cam_entry_test.vcd")
-    print("CamEntry Unit Test Success")