From: Segher Boessenkool Date: Mon, 20 May 2019 00:10:31 +0000 (+0200) Subject: rs6000: Delete the "wb" constraint X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=d17fbef89f753c171ab29c8a2c484fa2be8271b2;p=gcc.git rs6000: Delete the "wb" constraint This replaces the "wb" constraint by "v", with isa "p9v". * config/rs6000/constraints.md (define_register_constraint "wb"): Delete. * config/rs6000/rs6000.h (enum r6000_reg_class_enum): Delete RS6000_CONSTRAINT_wb. * config/rs6000/rs6000.c (rs6000_debug_reg_global): Adjust. (rs6000_init_hard_regno_mode_ok): Adjust. * config/rs6000/rs6000.md: Replace "wb" constraint by "v" with "p9v". * config/rs6000/vsx.md: Ditto. * doc/md.texi (Machine Constraints): Adjust. From-SVN: r271386 --- diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 170f8fc2ae4..19a683c276d 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,15 @@ +2019-05-19 Segher Boessenkool + + * config/rs6000/constraints.md (define_register_constraint "wb"): + Delete. + * config/rs6000/rs6000.h (enum r6000_reg_class_enum): Delete + RS6000_CONSTRAINT_wb. + * config/rs6000/rs6000.c (rs6000_debug_reg_global): Adjust. + (rs6000_init_hard_regno_mode_ok): Adjust. + * config/rs6000/rs6000.md: Replace "wb" constraint by "v" with "p9v". + * config/rs6000/vsx.md: Ditto. + * doc/md.texi (Machine Constraints): Adjust. + 2019-05-19 Segher Boessenkool * config/rs6000/constraints.md (define_register_constraint "wo"): diff --git a/gcc/config/rs6000/constraints.md b/gcc/config/rs6000/constraints.md index c11dc0eb65c..1bbfe714c21 100644 --- a/gcc/config/rs6000/constraints.md +++ b/gcc/config/rs6000/constraints.md @@ -56,9 +56,6 @@ (define_register_constraint "wa" "rs6000_constraints[RS6000_CONSTRAINT_wa]" "Any VSX register if the -mvsx option was used or NO_REGS.") -(define_register_constraint "wb" "rs6000_constraints[RS6000_CONSTRAINT_wb]" - "Altivec register if the -mpower9-dform option was used or NO_REGS.") - ;; NOTE: For compatibility, "wc" is reserved to represent individual CR bits. ;; It is currently used for that purpose in LLVM. diff --git a/gcc/config/rs6000/rs6000.c b/gcc/config/rs6000/rs6000.c index 18fa3acb2e1..f89a86ff5b7 100644 --- a/gcc/config/rs6000/rs6000.c +++ b/gcc/config/rs6000/rs6000.c @@ -2508,7 +2508,6 @@ rs6000_debug_reg_global (void) "f reg_class = %s\n" "v reg_class = %s\n" "wa reg_class = %s\n" - "wb reg_class = %s\n" "wd reg_class = %s\n" "we reg_class = %s\n" "wf reg_class = %s\n" @@ -2540,7 +2539,6 @@ rs6000_debug_reg_global (void) reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_f]], reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_v]], reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_wa]], - reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_wb]], reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_wd]], reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_we]], reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_wf]], @@ -3264,10 +3262,6 @@ rs6000_init_hard_regno_mode_ok (bool global_init_p) rs6000_constraints[RS6000_CONSTRAINT_wp] = VSX_REGS; /* TFmode */ } - /* Support for new D-form instructions. */ - if (TARGET_P9_VECTOR) - rs6000_constraints[RS6000_CONSTRAINT_wb] = ALTIVEC_REGS; - /* Support for new direct moves (ISA 3.0 + 64bit). */ if (TARGET_DIRECT_MOVE_128) rs6000_constraints[RS6000_CONSTRAINT_we] = VSX_REGS; diff --git a/gcc/config/rs6000/rs6000.h b/gcc/config/rs6000/rs6000.h index d59f4c702d3..2f2e45fd67f 100644 --- a/gcc/config/rs6000/rs6000.h +++ b/gcc/config/rs6000/rs6000.h @@ -1249,7 +1249,6 @@ enum r6000_reg_class_enum { RS6000_CONSTRAINT_f, /* fpr registers for single values */ RS6000_CONSTRAINT_v, /* Altivec registers */ RS6000_CONSTRAINT_wa, /* Any VSX register */ - RS6000_CONSTRAINT_wb, /* Altivec register if ISA 3.0 vector. */ RS6000_CONSTRAINT_wd, /* VSX register for V2DF */ RS6000_CONSTRAINT_we, /* VSX register if ISA 3.0 vector. */ RS6000_CONSTRAINT_wf, /* VSX register for V4SF */ diff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md index c56c58585fd..791aca783c5 100644 --- a/gcc/config/rs6000/rs6000.md +++ b/gcc/config/rs6000/rs6000.md @@ -477,7 +477,7 @@ (define_mode_attr f64_av [(DF "wv") (DD "wn")]) ; Definitions for 64-bit access to ISA 3.0 (power9) vector -(define_mode_attr f64_p9 [(DF "wb") (DD "wn")]) +(define_mode_attr f64_p9 [(DF "v") (DD "wn")]) ; These modes do not fit in integer registers in 32-bit mode. (define_mode_iterator DIFD [DI DF DD]) @@ -4769,7 +4769,7 @@ }) (define_insn_and_split "*extendsfdf2_fpr" - [(set (match_operand:DF 0 "gpc_reg_operand" "=d,?d,d,ws,?ws,wu,wb") + [(set (match_operand:DF 0 "gpc_reg_operand" "=d,?d,d,ws,?ws,wu,v") (float_extend:DF (match_operand:SF 1 "reg_or_mem_operand" "0,f,m,0,wy,Z,wY")))] "TARGET_HARD_FLOAT && !HONOR_SNANS (SFmode)" "@ @@ -4786,7 +4786,8 @@ emit_note (NOTE_INSN_DELETED); DONE; } - [(set_attr "type" "fp,fpsimple,fpload,fp,fpsimple,fpload,fpload")]) + [(set_attr "type" "fp,fpsimple,fpload,fp,fpsimple,fpload,fpload") + (set_attr "isa" "*,*,*,*,*,*,p9v")]) (define_insn "*extendsfdf2_snan" [(set (match_operand:DF 0 "gpc_reg_operand" "=d,ws") @@ -6945,18 +6946,15 @@ "=r, r, ?*wI, ?*wH, m, m, wY, Z, r, ?*wIwH, wIwH") - (unspec:SI [(match_operand:SF 1 "input_operand" "r, m, Z, Z, r, - f, wb, wu, wIwH, wIwH, + f, v, wu, wIwH, wIwH, r")] UNSPEC_SI_FROM_SF)) - (clobber (match_scratch:V4SF 2 "=X, X, X, X, X, X, X, X, wIwH, X, X"))] - "TARGET_NO_SF_SUBREG && (register_operand (operands[0], SImode) || register_operand (operands[1], SFmode))" @@ -6991,11 +6989,14 @@ "*, load, fpload, fpload, store, fpstore, fpstore, fpstore, mftgpr, fp, mffgpr") - (set_attr "length" "4, 4, 4, 4, 4, 4, 4, 4, 8, 4, - 4")]) + 4") + (set_attr "isa" + "*, *, *, *, *, + *, p9v, *, *, *, + *")]) ;; movsi_from_sf with zero extension ;; @@ -7280,11 +7281,11 @@ (define_insn "movsf_hardfloat" [(set (match_operand:SF 0 "nonimmediate_operand" - "=!r, f, wb, wu, m, wY, + "=!r, f, v, wu, m, wY, Z, m, ww, !r, f, ww, !r, *c*l, !r, *h") (match_operand:SF 1 "input_operand" - "m, m, wY, Z, f, wb, + "m, m, wY, Z, f, v, wu, r, j, j, f, ww, r, r, *h, 0"))] "(register_operand (operands[0], SFmode) @@ -7312,7 +7313,11 @@ [(set_attr "type" "load, fpload, fpload, fpload, fpstore, fpstore, fpstore, store, veclogical, integer, fpsimple, fpsimple, - *, mtjmpr, mfjmpr, *")]) + *, mtjmpr, mfjmpr, *") + (set_attr "isa" + "*, *, p9v, *, *, p9v, + *, *, *, *, *, *, + *, *, *, *")]) ;; LWZ LFIWZX STW STFIWX MTVSRWZ MFVSRWZ ;; FMR MR MT%0 MF%1 NOP @@ -7394,18 +7399,15 @@ ;; STXSIWX GPR->VSX VSX->GPR GPR->GPR (define_insn_and_split "movsf_from_si" [(set (match_operand:SF 0 "nonimmediate_operand" - "=!r, f, wb, wu, m, Z, + "=!r, f, v, wu, m, Z, Z, wy, ?r, !r") - (unspec:SF [(match_operand:SI 1 "input_operand" "m, m, wY, Z, r, f, wu, r, wy, r")] UNSPEC_SF_FROM_SI)) - (clobber (match_scratch:DI 2 "=X, X, X, X, X, X, X, r, X, X"))] - "TARGET_NO_SF_SUBREG && (register_operand (operands[0], SFmode) || register_operand (operands[1], SImode))" @@ -7442,7 +7444,10 @@ 4, 12, 4, 4") (set_attr "type" "load, fpload, fpload, fpload, store, fpstore, - fpstore, vecfloat, mffgpr, *")]) + fpstore, vecfloat, mffgpr, *") + (set_attr "isa" + "*, *, p9v, *, *, *, + *, *, *, *")]) ;; Move 64-bit binary/decimal floating point @@ -7546,12 +7551,10 @@ "=m, d, d, , wY, , Z, , , !r, Y, r, !r") - (match_operand:FMOVE64 1 "input_operand" "d, m, d, wY, , Z, , , , , r, Y, r"))] - "! TARGET_POWERPC64 && TARGET_HARD_FLOAT && (gpc_reg_operand (operands[0], mode) || gpc_reg_operand (operands[1], mode))" @@ -7573,12 +7576,15 @@ "fpstore, fpload, fpsimple, fpload, fpstore, fpload, fpstore, veclogical, veclogical, two, store, load, two") - (set_attr "size" "64") (set_attr "length" "4, 4, 4, 4, 4, 4, 4, 4, 4, 8, - 8, 8, 8")]) + 8, 8, 8") + (set_attr "isa" + "*, *, *, p9v, p9v, + *, *, *, *, *, + *, *, *")]) ;; STW LWZ MR G-const H-const F-const @@ -7613,13 +7619,11 @@ , Z, , , !r, YZ, r, !r, *c*l, !r, *h, r, wg, r, ") - (match_operand:FMOVE64 1 "input_operand" "d, m, d, wY, , Z, , , , , r, YZ, r, r, *h, 0, wg, r, , r"))] - "TARGET_POWERPC64 && TARGET_HARD_FLOAT && (gpc_reg_operand (operands[0], mode) || gpc_reg_operand (operands[1], mode))" @@ -7648,10 +7652,13 @@ "fpstore, fpload, fpsimple, fpload, fpstore, fpload, fpstore, veclogical, veclogical, integer, store, load, *, mtjmpr, mfjmpr, - *, mftgpr, mffgpr, mftgpr, mffgpr") - + *, mftgpr, mffgpr, mftgpr, mffgpr") (set_attr "size" "64") - (set_attr "length" "4")]) + (set_attr "isa" + "*, *, *, p9v, p9v, + *, *, *, *, *, + *, *, *, *, *, + *, *, *, *, *")]) ;; STD LD MR MT MF G-const ;; H-const F-const Special @@ -8708,16 +8715,14 @@ (define_insn "*movdi_internal32" [(set (match_operand:DI 0 "nonimmediate_operand" "=Y, r, r, m, ^d, ^d, - r, wY, Z, ^wb, $wv, ^wi, + r, wY, Z, ^v, $wv, ^wi, wa, wa, wv, wi, *i, wv, wv") - (match_operand:DI 1 "input_operand" "r, Y, r, ^d, m, ^d, - IJKnF, ^wb, $wv, wY, Z, ^wi, + IJKnF, ^v, $wv, wY, Z, ^wi, Oj, wM, OjwM, Oj, wM, wS, wB"))] - "! TARGET_POWERPC64 && (gpc_reg_operand (operands[0], DImode) || gpc_reg_operand (operands[1], DImode))" @@ -8754,7 +8759,7 @@ 4") (set_attr "isa" "*, *, *, *, *, *, - *, *, *, *, *, *, + *, p9v, *, p9v, *, *, p9v, p9v, *, *, *, *, *")]) @@ -8793,18 +8798,16 @@ (define_insn "*movdi_internal64" [(set (match_operand:DI 0 "nonimmediate_operand" "=YZ, r, r, r, r, r, - m, ^d, ^d, wY, Z, $wb, + m, ^d, ^d, wY, Z, $v, $wv, ^wi, wa, wa, wv, wi, wi, wv, wv, r, *h, *h, ?r, ?wg, ?r, ?wj") - (match_operand:DI 1 "input_operand" "r, YZ, r, I, L, nF, - ^d, m, ^d, ^wb, $wv, wY, + ^d, m, ^d, ^v, $wv, wY, Z, ^wi, Oj, wM, OjwM, Oj, wM, wS, wB, *h, r, 0, wg, r, wj, r"))] - "TARGET_POWERPC64 && (gpc_reg_operand (operands[0], DImode) || gpc_reg_operand (operands[1], DImode))" @@ -8843,7 +8846,6 @@ fpload, veclogical, vecsimple, vecsimple, vecsimple, veclogical, veclogical, vecsimple, vecsimple, mfjmpr, mtjmpr, *, mftgpr, mffgpr, mftgpr, mffgpr") - (set_attr "size" "64") (set_attr "length" "4, 4, 4, 4, 4, 20, @@ -8853,7 +8855,7 @@ 4, 4, 4, 4") (set_attr "isa" "*, *, *, *, *, *, - *, *, *, *, *, *, + *, *, *, p9v, *, p9v, *, *, p9v, p9v, *, *, *, *, *, *, *, *, *, *, *, *")]) diff --git a/gcc/config/rs6000/vsx.md b/gcc/config/rs6000/vsx.md index df8951e3555..0b2ddaae110 100644 --- a/gcc/config/rs6000/vsx.md +++ b/gcc/config/rs6000/vsx.md @@ -3280,14 +3280,15 @@ (define_insn "*vsx_extract__store" [(set (match_operand: 0 "memory_operand" "=m,Z,wY") (vec_select: - (match_operand:VSX_D 1 "register_operand" "d,wv,wb") + (match_operand:VSX_D 1 "register_operand" "d,wv,v") (parallel [(match_operand:QI 2 "vsx_scalar_64bit" "wD,wD,wD")])))] "VECTOR_MEM_VSX_P (mode)" "@ stfd%U0%X0 %1,%0 stxsdx %x1,%y0 stxsd %1,%0" - [(set_attr "type" "fpstore")]) + [(set_attr "type" "fpstore") + (set_attr "isa" "*,*,p9v")]) ;; Variable V2DI/V2DF extract shift (define_insn "vsx_vslo_" @@ -3352,7 +3353,7 @@ (set_attr "type" "fp")]) (define_insn_and_split "*vsx_extract_v4sf__load" - [(set (match_operand:SF 0 "register_operand" "=f,wv,wb,?r") + [(set (match_operand:SF 0 "register_operand" "=f,wv,v,?r") (vec_select:SF (match_operand:V4SF 1 "memory_operand" "m,Z,m,m") (parallel [(match_operand:QI 2 "const_0_to_3_operand" "n,n,n,n")]))) @@ -3366,7 +3367,8 @@ operands[3], SFmode); } [(set_attr "type" "fpload,fpload,fpload,load") - (set_attr "length" "8")]) + (set_attr "length" "8") + (set_attr "isa" "*,*,p9v,*")]) ;; Variable V4SF extract (define_insn_and_split "vsx_extract_v4sf_var" diff --git a/gcc/doc/md.texi b/gcc/doc/md.texi index dc58aa9d2b6..1debcabec3c 100644 --- a/gcc/doc/md.texi +++ b/gcc/doc/md.texi @@ -3246,9 +3246,6 @@ asm ("xsaddqp %x0,%x1,%x2" @noindent is incorrect. -@item wb -Altivec register if @option{-mcpu=power9} is used or NO_REGS. - @item wd VSX vector register to hold vector double data or NO_REGS.