From: Gabe Black <gblack@eecs.umich.edu>
Date: Sun, 8 Nov 2009 10:01:02 +0000 (-0800)
Subject: ARM: Add in more bits for the mon mode.
X-Git-Tag: stable_2012_02_02~1575^2~88
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=d188821d3700ee42e01fc43c9ef17568991fb3ff;p=gem5.git

ARM: Add in more bits for the mon mode.
---

diff --git a/src/arch/arm/isa.hh b/src/arch/arm/isa.hh
index 6341e6cd0..f8359679b 100644
--- a/src/arch/arm/isa.hh
+++ b/src/arch/arm/isa.hh
@@ -63,6 +63,9 @@ namespace ArmISA
               case MODE_SVC:
                 intRegMap = IntRegSvcMap;
                 break;
+              case MODE_MON:
+                intRegMap = IntRegMonMap;
+                break;
               case MODE_ABORT:
                 intRegMap = IntRegAbtMap;
                 break;
diff --git a/src/arch/arm/miscregs.hh b/src/arch/arm/miscregs.hh
index 3180669de..ba394d49c 100644
--- a/src/arch/arm/miscregs.hh
+++ b/src/arch/arm/miscregs.hh
@@ -59,6 +59,7 @@ namespace ArmISA
         MISCREG_SPSR_FIQ,
         MISCREG_SPSR_IRQ,
         MISCREG_SPSR_SVC,
+        MISCREG_SPSR_MON,
         MISCREG_SPSR_UND,
         MISCREG_SPSR_ABT,
         MISCREG_FPSR,
diff --git a/src/arch/arm/types.hh b/src/arch/arm/types.hh
index 2c4e1291c..d5cc07eaf 100644
--- a/src/arch/arm/types.hh
+++ b/src/arch/arm/types.hh
@@ -156,6 +156,7 @@ namespace ArmISA
         MODE_FIQ = 17,
         MODE_IRQ = 18,
         MODE_SVC = 19,
+        MODE_MON = 22,
         MODE_ABORT = 23,
         MODE_UNDEFINED = 27,
         MODE_SYSTEM = 31