From: Florent Kermarrec <florent@enjoy-digital.fr>
Date: Thu, 8 Jan 2015 21:58:26 +0000 (+0100)
Subject: use 166MHz clock
X-Git-Tag: 24jan2021_ls180~2572^2~63
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=d196a517d6c921fb27c6d877490d708a20d434ec;p=litex.git

use 166MHz clock
---

diff --git a/platforms/kc705.py b/platforms/kc705.py
index 0dcf075d..2884f910 100644
--- a/platforms/kc705.py
+++ b/platforms/kc705.py
@@ -128,7 +128,7 @@ def Platform(*args, toolchain="vivado", programmer="xc3sprog", **kwargs):
 			except ConstraintError:
 				pass
 			self.add_platform_command("""
-create_clock -name sys_clk -period 10 [get_nets sys_clk]
+create_clock -name sys_clk -period 6 [get_nets sys_clk]
 create_clock -name sata_rx_clk -period 6.66 [get_nets sata_rx_clk]
 create_clock -name sata_tx_clk -period 6.66 [get_nets sata_tx_clk]
 
diff --git a/targets/test.py b/targets/test.py
index b6346eb6..ee38e0d0 100644
--- a/targets/test.py
+++ b/targets/test.py
@@ -39,7 +39,7 @@ class _CRG(Module):
 				i_CLKIN1=clk200_se, i_CLKFBIN=pll_fb, o_CLKFBOUT=pll_fb,
 
 				# 100MHz
-				p_CLKOUT0_DIVIDE=10, p_CLKOUT0_PHASE=0.0, o_CLKOUT0=pll_sys,
+				p_CLKOUT0_DIVIDE=6, p_CLKOUT0_PHASE=0.0, o_CLKOUT0=pll_sys,
 
 				p_CLKOUT1_DIVIDE=2, p_CLKOUT1_PHASE=0.0, #o_CLKOUT1=,
 
@@ -110,7 +110,7 @@ class SimDesign(UART2WB):
 	default_platform = "kc705"
 
 	def __init__(self, platform, export_mila=False):
-		clk_freq = 100*1000000
+		clk_freq = 166*1000000
 		UART2WB.__init__(self, platform, clk_freq)
 		self.crg = _CRG(platform)
 
@@ -165,7 +165,7 @@ class TestDesign(UART2WB, AutoCSR):
 	csr_map.update(UART2WB.csr_map)
 
 	def __init__(self, platform, with_mila=True, export_mila=False):
-		clk_freq = 100*1000000
+		clk_freq = 166*1000000
 		UART2WB.__init__(self, platform, clk_freq)
 		self.crg = _CRG(platform)