From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Sun, 25 Jul 2021 15:01:13 +0000 (+0100)
Subject: update to openlane-nmigen fork (thx lethalbit)
X-Git-Tag: DRAFT_SVP64_0_1~588
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=d19b86b9b6f20e8119b7d21a6a1281ea1b69dd93;p=libreriscv.git

update to openlane-nmigen fork (thx lethalbit)
---

diff --git a/resources.mdwn b/resources.mdwn
index f7a1e0ea3..155c2f271 100644
--- a/resources.mdwn
+++ b/resources.mdwn
@@ -350,7 +350,7 @@ Some learning resources I found in the community:
   Understanding Latency Hiding on GPUs, by Vasily Volkov
 * Efabless "Openlane" <https://github.com/efabless/openlane>
 * example of openlane with nmigen
-  <https://gist.github.com/lethalbit/e65e296bc6a3810280d1b256c9df591b>
+  <https://github.com/lethalbit/nmigen/tree/openlane>
 * Co-simulation plugin for verilator, transferring to ECP5
   <https://github.com/vmware/cascade>
 * Multi-read/write ported memories