From: Miodrag Milanovic <mmicko@gmail.com>
Date: Fri, 4 Oct 2019 06:41:53 +0000 (+0200)
Subject: Removed alu and div_mod tests as agreed
X-Git-Tag: working-ls180~989^2~8
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=d19f765a581ac465a7f7cea22f1d96c9da9cbe01;p=yosys.git

Removed alu and div_mod tests as agreed
---

diff --git a/tests/ecp5/alu.v b/tests/ecp5/alu.v
deleted file mode 100644
index f82cc2e21..000000000
--- a/tests/ecp5/alu.v
+++ /dev/null
@@ -1,19 +0,0 @@
-module top (
-	input clock,
-	input [31:0] dinA, dinB,
-	input [2:0] opcode,
-	output reg [31:0] dout
-);
-	always @(posedge clock) begin
-		case (opcode)
-		0: dout <= dinA + dinB;
-		1: dout <= dinA - dinB;
-		2: dout <= dinA >> dinB;
-		3: dout <= $signed(dinA) >>> dinB;
-		4: dout <= dinA << dinB;
-		5: dout <= dinA & dinB;
-		6: dout <= dinA | dinB;
-		7: dout <= dinA ^ dinB;
-		endcase
-	end
-endmodule
diff --git a/tests/ecp5/alu.ys b/tests/ecp5/alu.ys
deleted file mode 100644
index c2950b164..000000000
--- a/tests/ecp5/alu.ys
+++ /dev/null
@@ -1,13 +0,0 @@
-read_verilog alu.v
-hierarchy -top top
-proc
-flatten
-equiv_opt -assert -map +/ecp5/cells_sim.v synth_ecp5 # equivalency check
-design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
-cd top # Constrain all select calls below inside the top module
-select -assert-count 32 t:CCU2C
-select -assert-count 242 t:L6MUX21
-select -assert-count 1127 t:LUT4
-select -assert-count 417 t:PFUMX
-select -assert-count 32 t:TRELLIS_FF
-select -assert-none t:CCU2C t:L6MUX21 t:LUT4 t:PFUMX t:TRELLIS_FF %% t:* %D
diff --git a/tests/ecp5/div_mod.v b/tests/ecp5/div_mod.v
deleted file mode 100644
index 64a36707d..000000000
--- a/tests/ecp5/div_mod.v
+++ /dev/null
@@ -1,13 +0,0 @@
-module top
-(
- input [3:0] x,
- input [3:0] y,
-
- output [3:0] A,
- output [3:0] B
- );
-
-assign A =  x % y;
-assign B =  x / y;
-
-endmodule
diff --git a/tests/ecp5/div_mod.ys b/tests/ecp5/div_mod.ys
deleted file mode 100644
index 9efb00701..000000000
--- a/tests/ecp5/div_mod.ys
+++ /dev/null
@@ -1,12 +0,0 @@
-read_verilog div_mod.v
-hierarchy -top top
-flatten
-equiv_opt -assert -map +/ecp5/cells_sim.v synth_ecp5 # equivalency check
-design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
-cd top # Constrain all select calls below inside the top module
-
-select -assert-count 28 t:CCU2C
-select -assert-count 26 t:L6MUX21
-select -assert-count 138 t:LUT4
-select -assert-count 60 t:PFUMX
-select -assert-none t:LUT4 t:CCU2C t:L6MUX21 t:PFUMX %% t:* %D