From: Samuel Pitoiset Date: Fri, 17 Jul 2020 20:51:34 +0000 (+0200) Subject: radv: disable CPU caching for IBS to reduce fetch latency X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=d1bba2eee79beceff785e4e00108ba46dd167ef3;p=mesa.git radv: disable CPU caching for IBS to reduce fetch latency AMDGPU_GEM_CREATE_CPU_GTT_USWC should be faster when CPU reads are unexpected (because they aren't cached). Signed-off-by: Samuel Pitoiset Reviewed-by: Bas Nieuwenhuizen Part-of: --- diff --git a/src/amd/vulkan/si_cmd_buffer.c b/src/amd/vulkan/si_cmd_buffer.c index 553ea2dfa83..3ec23fc93a5 100644 --- a/src/amd/vulkan/si_cmd_buffer.c +++ b/src/amd/vulkan/si_cmd_buffer.c @@ -530,7 +530,8 @@ cik_create_gfx_config(struct radv_device *device) RADEON_DOMAIN_GTT, RADEON_FLAG_CPU_ACCESS| RADEON_FLAG_NO_INTERPROCESS_SHARING | - RADEON_FLAG_READ_ONLY, + RADEON_FLAG_READ_ONLY | + RADEON_FLAG_GTT_WC, RADV_BO_PRIORITY_CS); if (!device->gfx_init) goto fail; diff --git a/src/amd/vulkan/winsys/amdgpu/radv_amdgpu_cs.c b/src/amd/vulkan/winsys/amdgpu/radv_amdgpu_cs.c index 23185fd5c43..15c55a7bf31 100644 --- a/src/amd/vulkan/winsys/amdgpu/radv_amdgpu_cs.c +++ b/src/amd/vulkan/winsys/amdgpu/radv_amdgpu_cs.c @@ -324,7 +324,8 @@ radv_amdgpu_cs_create(struct radeon_winsys *ws, RADEON_DOMAIN_GTT, RADEON_FLAG_CPU_ACCESS | RADEON_FLAG_NO_INTERPROCESS_SHARING | - RADEON_FLAG_READ_ONLY, + RADEON_FLAG_READ_ONLY | + RADEON_FLAG_GTT_WC, RADV_BO_PRIORITY_CS); if (!cs->ib_buffer) { free(cs); @@ -440,7 +441,8 @@ static void radv_amdgpu_cs_grow(struct radeon_cmdbuf *_cs, size_t min_size) RADEON_DOMAIN_GTT, RADEON_FLAG_CPU_ACCESS | RADEON_FLAG_NO_INTERPROCESS_SHARING | - RADEON_FLAG_READ_ONLY, + RADEON_FLAG_READ_ONLY | + RADEON_FLAG_GTT_WC, RADV_BO_PRIORITY_CS); if (!cs->ib_buffer) {