From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Sat, 28 Mar 2020 17:54:47 +0000 (+0000)
Subject: add ldst mul
X-Git-Tag: convert-csv-opcode-to-binary~3039
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=d1bf6c891386d75e2f51d01ced04b44b59c4fbb4;p=libreriscv.git

add ldst mul
---

diff --git a/openpower/isa/fixedload.mdwn b/openpower/isa/fixedload.mdwn
index a6651befd..4ffe9ce04 100644
--- a/openpower/isa/fixedload.mdwn
+++ b/openpower/isa/fixedload.mdwn
@@ -237,4 +237,17 @@ ldbrx RT,RA,RB
     || load_data[24:31 || load_data[16:23]
     || load_data[8:15  || load_data[0:7]
 
+# Load Multiple Word
+
+lmw RT,D(RA)
+
+    if RA = 0 then b <-  0
+    else           b <-  (RA)
+    EA <- b + EXTS(D)
+    r <- RT
+    do while r <=  31
+        GPR(r) <- [0]*32 || MEM(EA, 4)
+        r <- r + 1
+        EA <- EA + 4
+
 
diff --git a/openpower/isa/fixedstore.mdwn b/openpower/isa/fixedstore.mdwn
index 41e1a931e..9a6df9d22 100644
--- a/openpower/isa/fixedstore.mdwn
+++ b/openpower/isa/fixedstore.mdwn
@@ -173,4 +173,17 @@ stdbrx RS,RA,RB
     || (RS)[24:31] || (RS)[16:23]
     || (RS)[8:15]  || (RS)[0:7]
 
+# Store Multiple Word
+
+stmw RS,D(RA)
+
+    if RA = 0 then b <- 0
+    else           b <- (RA)
+    EA <- b + EXTS(D)
+    r <- RS
+    do while r <= 31
+        MEM(EA, 4) <- GPR(r)[32:63]
+        r <-  r + 1
+        EA <-  EA + 4
+