From: H.J. Lu Date: Mon, 5 May 2008 21:34:17 +0000 (-0700) Subject: i386.md (sat_plusminus): New. X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=d1c3b58718a703958d4f1756e5adf0ed7d0c32e5;p=gcc.git i386.md (sat_plusminus): New. 2008-05-05 H.J. Lu * config/i386/i386.md (sat_plusminus): New. (plusminus_insn): Likewise. (plusminus_mnemonic): Likewise. (addsub): Removed. (comm): Add ss_plus, us_plus, ss_minus and us_minus. (*3_cc_overflow): Renamed to ... (*3_cc_overflow): This. (*si3_zext_cc_overflow): Renamed to ... (*si3_zext_cc_overflow): This. * gcc/config/i386/sse.md (3): Renamed to ... (3): This. (*3): Renamed to ... (*3): This. (_vm3): Renamed to ... (_vm3): This. (sse3_hv4sf3): Renamed to ... (sse3_hv4sf3): This. (sse3_hv2df3): Renamed to ... (sse3_hv2df3): This. (3): New. (*3): Likewise. (sse2_3): Likewise. (add): Removed. (*add3): Likewise. (sse2_ssadd3): Likewise. (sse2_usadd3): Likewise. (sub3): Likewise. (*sub3): Likewise. (sse2_sssub3): Likewise. (sse2_ussub3): Likewise. From-SVN: r134957 --- diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 8f91827189b..c9771d2327f 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,14 +1,48 @@ +2008-05-05 H.J. Lu + + * config/i386/i386.md (sat_plusminus): New. + (plusminus_insn): Likewise. + (plusminus_mnemonic): Likewise. + (addsub): Removed. + (comm): Add ss_plus, us_plus, ss_minus and us_minus. + (*3_cc_overflow): Renamed to ... + (*3_cc_overflow): This. + (*si3_zext_cc_overflow): Renamed to ... + (*si3_zext_cc_overflow): This. + + * gcc/config/i386/sse.md (3): Renamed to ... + (3): This. + (*3): Renamed to ... + (*3): This. + (_vm3): Renamed to ... + (_vm3): This. + (sse3_hv4sf3): Renamed to ... + (sse3_hv4sf3): This. + (sse3_hv2df3): Renamed to ... + (sse3_hv2df3): This. + (3): New. + (*3): Likewise. + (sse2_3): Likewise. + (add): Removed. + (*add3): Likewise. + (sse2_ssadd3): Likewise. + (sse2_usadd3): Likewise. + (sub3): Likewise. + (*sub3): Likewise. + (sse2_sssub3): Likewise. + (sse2_ussub3): Likewise. + 2008-05-05 Benjamin Kosnik - * gthr-single.h: Add in required interface elements as per gthr.h. - Add stub types for __gthread_key_t, __gthread_once_t. Add defines - for __GTHREAD_ONCE_INIT, __GTHREAD_RECURSIVE_MUTEX_INIT. - Generalize UNUSED macro. - (__gthread_once): Add. - (__gthread_key_create): Add. - (__gthread_key_delete): Add. - (__gthread_getspecific): Add. - (__gthread_setspecific): Add. + * gthr-single.h: Add in required interface elements as per gthr.h. + Add stub types for __gthread_key_t, __gthread_once_t. Add defines + for __GTHREAD_ONCE_INIT, __GTHREAD_RECURSIVE_MUTEX_INIT. + Generalize UNUSED macro. + (__gthread_once): Add. + (__gthread_key_create): Add. + (__gthread_key_delete): Add. + (__gthread_getspecific): Add. + (__gthread_setspecific): Add. 2008-05-05 Andrew Pinski diff --git a/gcc/config/i386/i386.md b/gcc/config/i386/i386.md index 2a8c16ec60b..b5e9082ceec 100644 --- a/gcc/config/i386/i386.md +++ b/gcc/config/i386/i386.md @@ -535,11 +535,21 @@ (define_code_iterator plusminus [plus minus]) -;; Base name for define_insn and insn mnemonic. -(define_code_attr addsub [(plus "add") (minus "sub")]) +(define_code_iterator sat_plusminus [ss_plus us_plus ss_minus us_minus]) + +;; Base name for define_insn +(define_code_attr plusminus_insn + [(plus "add") (ss_plus "ssadd") (us_plus "usadd") + (minus "sub") (ss_minus "sssub") (us_minus "ussub")]) + +;; Base name for insn mnemonic. +(define_code_attr plusminus_mnemonic + [(plus "add") (ss_plus "adds") (us_plus "addus") + (minus "sub") (ss_minus "subs") (us_minus "subus")]) ;; Mark commutative operators as such in constraints. -(define_code_attr comm [(plus "%") (minus "")]) +(define_code_attr comm [(plus "%") (ss_plus "%") (us_plus "%") + (minus "") (ss_minus "") (us_minus "")]) ;; Mapping of signed max and min (define_code_iterator smaxmin [smax smin]) @@ -5582,7 +5592,7 @@ [(set_attr "type" "alu") (set_attr "mode" "DI")]) -(define_insn "*3_cc_overflow" +(define_insn "*3_cc_overflow" [(set (reg:CCC FLAGS_REG) (compare:CCC (plusminus:SWI @@ -5592,7 +5602,7 @@ (set (match_operand:SWI 0 "nonimmediate_operand" "=m,") (plusminus:SWI (match_dup 1) (match_dup 2)))] "ix86_binary_operator_ok (, mode, operands)" - "{}\t{%2, %0|%0, %2}" + "{}\t{%2, %0|%0, %2}" [(set_attr "type" "alu") (set_attr "mode" "")]) @@ -5619,7 +5629,7 @@ [(set_attr "type" "icmp") (set_attr "mode" "")]) -(define_insn "*si3_zext_cc_overflow" +(define_insn "*si3_zext_cc_overflow" [(set (reg:CCC FLAGS_REG) (compare:CCC (plusminus:SI (match_operand:SI 1 "nonimmediate_operand" "0") @@ -5628,7 +5638,7 @@ (set (match_operand:DI 0 "register_operand" "=r") (zero_extend:DI (plusminus:SI (match_dup 1) (match_dup 2))))] "TARGET_64BIT && ix86_binary_operator_ok (, SImode, operands)" - "{l}\t{%2, %k0|%k0, %2}" + "{l}\t{%2, %k0|%k0, %2}" [(set_attr "type" "alu") (set_attr "mode" "SI")]) diff --git a/gcc/config/i386/sse.md b/gcc/config/i386/sse.md index 4a4260d9a15..a6c7a07de49 100644 --- a/gcc/config/i386/sse.md +++ b/gcc/config/i386/sse.md @@ -302,7 +302,7 @@ "SSE_VEC_FLOAT_MODE_P (mode)" "ix86_expand_fp_absneg_operator (, mode, operands); DONE;") -(define_expand "3" +(define_expand "3" [(set (match_operand:SSEMODEF2P 0 "register_operand" "") (plusminus:SSEMODEF2P (match_operand:SSEMODEF2P 1 "nonimmediate_operand" "") @@ -310,18 +310,18 @@ "SSE_VEC_FLOAT_MODE_P (mode)" "ix86_fixup_binary_operands_no_copy (, mode, operands);") -(define_insn "*3" +(define_insn "*3" [(set (match_operand:SSEMODEF2P 0 "register_operand" "=x") (plusminus:SSEMODEF2P (match_operand:SSEMODEF2P 1 "nonimmediate_operand" "0") (match_operand:SSEMODEF2P 2 "nonimmediate_operand" "xm")))] "SSE_VEC_FLOAT_MODE_P (mode) && ix86_binary_operator_ok (, mode, operands)" - "p\t{%2, %0|%0, %2}" + "p\t{%2, %0|%0, %2}" [(set_attr "type" "sseadd") (set_attr "mode" "")]) -(define_insn "_vm3" +(define_insn "_vm3" [(set (match_operand:SSEMODEF2P 0 "register_operand" "=x") (vec_merge:SSEMODEF2P (plusminus:SSEMODEF2P @@ -331,7 +331,7 @@ (const_int 1)))] "SSE_VEC_FLOAT_MODE_P (mode) && ix86_binary_operator_ok (, V4SFmode, operands)" - "s\t{%2, %0|%0, %2}" + "s\t{%2, %0|%0, %2}" [(set_attr "type" "sseadd") (set_attr "mode" "")]) @@ -615,7 +615,7 @@ [(set_attr "type" "sseadd") (set_attr "mode" "V2DF")]) -(define_insn "sse3_hv4sf3" +(define_insn "sse3_hv4sf3" [(set (match_operand:V4SF 0 "register_operand" "=x") (vec_concat:V4SF (vec_concat:V2SF @@ -637,12 +637,12 @@ (vec_select:SF (match_dup 2) (parallel [(const_int 2)])) (vec_select:SF (match_dup 2) (parallel [(const_int 3)]))))))] "TARGET_SSE3" - "hps\t{%2, %0|%0, %2}" + "hps\t{%2, %0|%0, %2}" [(set_attr "type" "sseadd") (set_attr "prefix_rep" "1") (set_attr "mode" "V4SF")]) -(define_insn "sse3_hv2df3" +(define_insn "sse3_hv2df3" [(set (match_operand:V2DF 0 "register_operand" "=x") (vec_concat:V2DF (plusminus:DF @@ -656,7 +656,7 @@ (parallel [(const_int 0)])) (vec_select:DF (match_dup 2) (parallel [(const_int 1)])))))] "TARGET_SSE3" - "hpd\t{%2, %0|%0, %2}" + "hpd\t{%2, %0|%0, %2}" [(set_attr "type" "sseadd") (set_attr "mode" "V2DF")]) @@ -2722,82 +2722,32 @@ "TARGET_SSE2" "operands[2] = force_reg (mode, CONST0_RTX (mode));") -(define_expand "add3" +(define_expand "3" [(set (match_operand:SSEMODEI 0 "register_operand" "") - (plus:SSEMODEI (match_operand:SSEMODEI 1 "nonimmediate_operand" "") - (match_operand:SSEMODEI 2 "nonimmediate_operand" "")))] - "TARGET_SSE2" - "ix86_fixup_binary_operands_no_copy (PLUS, mode, operands);") - -(define_insn "*add3" - [(set (match_operand:SSEMODEI 0 "register_operand" "=x") - (plus:SSEMODEI - (match_operand:SSEMODEI 1 "nonimmediate_operand" "%0") - (match_operand:SSEMODEI 2 "nonimmediate_operand" "xm")))] - "TARGET_SSE2 && ix86_binary_operator_ok (PLUS, mode, operands)" - "padd\t{%2, %0|%0, %2}" - [(set_attr "type" "sseiadd") - (set_attr "prefix_data16" "1") - (set_attr "mode" "TI")]) - -(define_insn "sse2_ssadd3" - [(set (match_operand:SSEMODE12 0 "register_operand" "=x") - (ss_plus:SSEMODE12 - (match_operand:SSEMODE12 1 "nonimmediate_operand" "%0") - (match_operand:SSEMODE12 2 "nonimmediate_operand" "xm")))] - "TARGET_SSE2 && ix86_binary_operator_ok (SS_PLUS, mode, operands)" - "padds\t{%2, %0|%0, %2}" - [(set_attr "type" "sseiadd") - (set_attr "prefix_data16" "1") - (set_attr "mode" "TI")]) - -(define_insn "sse2_usadd3" - [(set (match_operand:SSEMODE12 0 "register_operand" "=x") - (us_plus:SSEMODE12 - (match_operand:SSEMODE12 1 "nonimmediate_operand" "%0") - (match_operand:SSEMODE12 2 "nonimmediate_operand" "xm")))] - "TARGET_SSE2 && ix86_binary_operator_ok (US_PLUS, mode, operands)" - "paddus\t{%2, %0|%0, %2}" - [(set_attr "type" "sseiadd") - (set_attr "prefix_data16" "1") - (set_attr "mode" "TI")]) - -(define_expand "sub3" - [(set (match_operand:SSEMODEI 0 "register_operand" "") - (minus:SSEMODEI (match_operand:SSEMODEI 1 "register_operand" "") - (match_operand:SSEMODEI 2 "nonimmediate_operand" "")))] + (plusminus:SSEMODEI + (match_operand:SSEMODEI 1 "nonimmediate_operand" "") + (match_operand:SSEMODEI 2 "nonimmediate_operand" "")))] "TARGET_SSE2" - "ix86_fixup_binary_operands_no_copy (MINUS, mode, operands);") + "ix86_fixup_binary_operands_no_copy (, mode, operands);") -(define_insn "*sub3" +(define_insn "*3" [(set (match_operand:SSEMODEI 0 "register_operand" "=x") - (minus:SSEMODEI - (match_operand:SSEMODEI 1 "register_operand" "0") + (plusminus:SSEMODEI + (match_operand:SSEMODEI 1 "nonimmediate_operand" "0") (match_operand:SSEMODEI 2 "nonimmediate_operand" "xm")))] - "TARGET_SSE2" - "psub\t{%2, %0|%0, %2}" - [(set_attr "type" "sseiadd") - (set_attr "prefix_data16" "1") - (set_attr "mode" "TI")]) - -(define_insn "sse2_sssub3" - [(set (match_operand:SSEMODE12 0 "register_operand" "=x") - (ss_minus:SSEMODE12 - (match_operand:SSEMODE12 1 "register_operand" "0") - (match_operand:SSEMODE12 2 "nonimmediate_operand" "xm")))] - "TARGET_SSE2" - "psubs\t{%2, %0|%0, %2}" + "TARGET_SSE2 && ix86_binary_operator_ok (, mode, operands)" + "p\t{%2, %0|%0, %2}" [(set_attr "type" "sseiadd") (set_attr "prefix_data16" "1") (set_attr "mode" "TI")]) -(define_insn "sse2_ussub3" +(define_insn "sse2_3" [(set (match_operand:SSEMODE12 0 "register_operand" "=x") - (us_minus:SSEMODE12 - (match_operand:SSEMODE12 1 "register_operand" "0") + (sat_plusminus:SSEMODE12 + (match_operand:SSEMODE12 1 "nonimmediate_operand" "0") (match_operand:SSEMODE12 2 "nonimmediate_operand" "xm")))] - "TARGET_SSE2" - "psubus\t{%2, %0|%0, %2}" + "TARGET_SSE2 && ix86_binary_operator_ok (, mode, operands)" + "p\t{%2, %0|%0, %2}" [(set_attr "type" "sseiadd") (set_attr "prefix_data16" "1") (set_attr "mode" "TI")])