From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Wed, 8 Dec 2021 16:42:32 +0000 (+0000)
Subject: remove MSR and add CIA to MMU Input Record
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=d1df8e61d9b2da83557bdc5f92838a9b625e30db;p=soc.git

remove MSR and add CIA to MMU Input Record
---

diff --git a/src/soc/fu/mmu/mmu_input_record.py b/src/soc/fu/mmu/mmu_input_record.py
index 109d2d38..281e8dd8 100644
--- a/src/soc/fu/mmu/mmu_input_record.py
+++ b/src/soc/fu/mmu/mmu_input_record.py
@@ -13,7 +13,7 @@ class CompMMUOpSubset(CompOpSubsetBase):
         layout = (('insn_type', MicrOp),
                   ('fn_unit', Function),
                   ('insn', 32),
-                  ('msr', 64), # TODO: a lot less bits.  only need PR, DR, SF
+                  ('cia', 64), # for instruction fault (MMU PTE lookup)
                   ('zero_a', 1),
                   )
         super().__init__(layout, name=name)