From: Dmitry Selyutin Date: Tue, 11 Apr 2023 18:27:23 +0000 (+0300) Subject: ppc/svp64: support absd instructions X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=d1e2521ebcb92d127f827f80b2443b2e057e2d39;p=binutils-gdb.git ppc/svp64: support absd instructions --- diff --git a/gas/testsuite/gas/ppc/absd.d b/gas/testsuite/gas/ppc/absd.d new file mode 100644 index 00000000000..f0eae5780c7 --- /dev/null +++ b/gas/testsuite/gas/ppc/absd.d @@ -0,0 +1,32 @@ +#as: -mlibresoc +#objdump: -dr -Mlibresoc + +.*: file format .* + + +Disassembly of section \.text: +0+ <\.text>: +.*:\s+(5b e0 03 ec|ec 03 e0 5b)\s+absdacs\s+r31,r0,r0 +.*:\s+(58 1f 03 ec|ec 03 1f 58)\s+absdacs\s+r0,r31,r0 +.*:\s+(58 00 fb ec|ec fb 00 58)\s+absdacs\s+r0,r0,r31 +.*:\s+(5b e0 03 ed|ed 03 e0 5b)\s+absdacs.\s+r31,r0,r0 +.*:\s+(58 1f 03 ed|ed 03 1f 58)\s+absdacs.\s+r0,r31,r0 +.*:\s+(58 00 fb ed|ed fb 00 58)\s+absdacs.\s+r0,r0,r31 +.*:\s+(5b e0 04 ec|ec 04 e0 5b)\s+absds\s+r31,r0,r0 +.*:\s+(58 1f 04 ec|ec 04 1f 58)\s+absds\s+r0,r31,r0 +.*:\s+(58 00 fc ec|ec fc 00 58)\s+absds\s+r0,r0,r31 +.*:\s+(5b e0 04 ed|ed 04 e0 5b)\s+absds.\s+r31,r0,r0 +.*:\s+(58 1f 04 ed|ed 04 1f 58)\s+absds.\s+r0,r31,r0 +.*:\s+(58 00 fc ed|ed fc 00 58)\s+absds.\s+r0,r0,r31 +.*:\s+(5b e0 05 ec|ec 05 e0 5b)\s+absdu\s+r31,r0,r0 +.*:\s+(58 1f 05 ec|ec 05 1f 58)\s+absdu\s+r0,r31,r0 +.*:\s+(58 00 fd ec|ec fd 00 58)\s+absdu\s+r0,r0,r31 +.*:\s+(5b e0 05 ed|ed 05 e0 5b)\s+absdu.\s+r31,r0,r0 +.*:\s+(58 1f 05 ed|ed 05 1f 58)\s+absdu.\s+r0,r31,r0 +.*:\s+(58 00 fd ed|ed fd 00 58)\s+absdu.\s+r0,r0,r31 +.*:\s+(5b e0 07 ec|ec 07 e0 5b)\s+absdacu\s+r31,r0,r0 +.*:\s+(58 1f 07 ec|ec 07 1f 58)\s+absdacu\s+r0,r31,r0 +.*:\s+(58 00 ff ec|ec ff 00 58)\s+absdacu\s+r0,r0,r31 +.*:\s+(5b e0 07 ed|ed 07 e0 5b)\s+absdacu.\s+r31,r0,r0 +.*:\s+(58 1f 07 ed|ed 07 1f 58)\s+absdacu.\s+r0,r31,r0 +.*:\s+(58 00 ff ed|ed ff 00 58)\s+absdacu.\s+r0,r0,r31 diff --git a/gas/testsuite/gas/ppc/absd.s b/gas/testsuite/gas/ppc/absd.s new file mode 100644 index 00000000000..c7f173d8aef --- /dev/null +++ b/gas/testsuite/gas/ppc/absd.s @@ -0,0 +1,24 @@ +absdacs 31,0,0 +absdacs 0,31,0 +absdacs 0,0,31 +absdacs. 31,0,0 +absdacs. 0,31,0 +absdacs. 0,0,31 +absds 31,0,0 +absds 0,31,0 +absds 0,0,31 +absds. 31,0,0 +absds. 0,31,0 +absds. 0,0,31 +absdu 31,0,0 +absdu 0,31,0 +absdu 0,0,31 +absdu. 31,0,0 +absdu. 0,31,0 +absdu. 0,0,31 +absdacu 31,0,0 +absdacu 0,31,0 +absdacu 0,0,31 +absdacu. 31,0,0 +absdacu. 0,31,0 +absdacu. 0,0,31 diff --git a/gas/testsuite/gas/ppc/ppc.exp b/gas/testsuite/gas/ppc/ppc.exp index 77a860fd046..8918ec8d36b 100644 --- a/gas/testsuite/gas/ppc/ppc.exp +++ b/gas/testsuite/gas/ppc/ppc.exp @@ -166,3 +166,4 @@ run_dump_test "fishmv" run_dump_test "minmax" run_dump_test "avgadd" run_dump_test "cprop" +run_dump_test "absd" diff --git a/opcodes/ppc-opc.c b/opcodes/ppc-opc.c index 734e025c5f5..333b8964fa1 100644 --- a/opcodes/ppc-opc.c +++ b/opcodes/ppc-opc.c @@ -7044,6 +7044,15 @@ const struct powerpc_opcode powerpc_opcodes[] = { {"cprop", XRC(22,398,0), X_MASK, SVP64, PPCVLE, {RT, RA, RB}}, {"cprop.", XRC(22,398,1), X_MASK, SVP64, PPCVLE, {RT, RA, RB}}, +{"absdacs", XRC(22,502,0), X_MASK, SVP64, PPCVLE, {RT, RA, RB}}, +{"absdacs.", XRC(22,502,1), X_MASK, SVP64, PPCVLE, {RT, RA, RB}}, +{"absds", XRC(22,630,0), X_MASK, SVP64, PPCVLE, {RT, RA, RB}}, +{"absds.", XRC(22,630,1), X_MASK, SVP64, PPCVLE, {RT, RA, RB}}, +{"absdu", XRC(22,758,0), X_MASK, SVP64, PPCVLE, {RT, RA, RB}}, +{"absdu.", XRC(22,758,1), X_MASK, SVP64, PPCVLE, {RT, RA, RB}}, +{"absdacu", XRC(22,1014,0), X_MASK, SVP64, PPCVLE, {RT, RA, RB}}, +{"absdacu.", XRC(22,1014,1), X_MASK, SVP64, PPCVLE, {RT, RA, RB}}, + {"avgadd", XRC(22,846,0), X_MASK, SVP64, PPCVLE, {RT, RA, RB}}, {"avgadd.", XRC(22,846,1), X_MASK, SVP64, PPCVLE, {RT, RA, RB}},