From: H.J. Lu <hongjiu.lu@intel.com>
Date: Mon, 20 Jun 2011 14:53:48 +0000 (+0000)
Subject: Check zero/sign extended hard registers.
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=d1e32c4a411c4a216b7d80e56da2b8a73197505e;p=gcc.git

Check zero/sign extended hard registers.

2011-06-20  H.J. Lu  <hongjiu.lu@intel.com>

	PR middle-end/47725
	* combine.c (cant_combine_insn_p): Check zero/sign extended
	hard registers.

From-SVN: r175218
---

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index aa9449b737b..a4b5faf714c 100644
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,9 @@
+2011-06-20  H.J. Lu  <hongjiu.lu@intel.com>
+
+	PR middle-end/47725
+	* combine.c (cant_combine_insn_p): Check zero/sign extended
+	hard registers.
+
 2011-06-20  Ramana Radhakrishnan  <ramana.radhakrishnan@linaro.org>
 
 	PR target/49385
diff --git a/gcc/combine.c b/gcc/combine.c
index 56fb44eaf42..004ae27687d 100644
--- a/gcc/combine.c
+++ b/gcc/combine.c
@@ -2168,6 +2168,12 @@ cant_combine_insn_p (rtx insn)
     return 0;
   src = SET_SRC (set);
   dest = SET_DEST (set);
+  if (GET_CODE (src) == ZERO_EXTEND
+      || GET_CODE (src) == SIGN_EXTEND)
+    src = XEXP (src, 0);
+  if (GET_CODE (dest) == ZERO_EXTEND
+      || GET_CODE (dest) == SIGN_EXTEND)
+    dest = XEXP (dest, 0);
   if (GET_CODE (src) == SUBREG)
     src = SUBREG_REG (src);
   if (GET_CODE (dest) == SUBREG)