From: Clifford Wolf <clifford@clifford.at>
Date: Wed, 7 Jan 2015 00:59:36 +0000 (+0100)
Subject: More Xilinx bram cleanups
X-Git-Tag: yosys-0.5~118
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=d1e38693d59b09f374f6228735932a347c3018b3;p=yosys.git

More Xilinx bram cleanups
---

diff --git a/techlibs/xilinx/brams.v b/techlibs/xilinx/brams.v
index 83f2aede4..d9d5391b3 100644
--- a/techlibs/xilinx/brams.v
+++ b/techlibs/xilinx/brams.v
@@ -50,8 +50,8 @@ module \$__XILINX_RAMB36_SDP72 (CLK2, CLK3, A1ADDR, A1DATA, B1ADDR, B1DATA, B1EN
 		.RAM_MODE("SDP"),
 		.READ_WIDTH_A(72),
 		.WRITE_WIDTH_B(72),
-		.WRITE_MODE_A(TRANSP2 ? "WRITE_FIRST" : "READ_FIRST"),
-		.WRITE_MODE_B(TRANSP2 ? "WRITE_FIRST" : "READ_FIRST")
+		.WRITE_MODE_A("READ_FIRST"),
+		.WRITE_MODE_B("READ_FIRST")
 	) _TECHMAP_REPLACE_ (
 		.DOBDO(DO[63:32]),
 		.DOADO(DO[31:0]),
@@ -127,8 +127,8 @@ module \$__XILINX_RAMB18_SDP36 (CLK2, CLK3, A1ADDR, A1DATA, B1ADDR, B1DATA, B1EN
 		.RAM_MODE("SDP"),
 		.READ_WIDTH_A(36),
 		.WRITE_WIDTH_B(36),
-		.WRITE_MODE_A(TRANSP2 ? "WRITE_FIRST" : "READ_FIRST"),
-		.WRITE_MODE_B(TRANSP2 ? "WRITE_FIRST" : "READ_FIRST")
+		.WRITE_MODE_A("READ_FIRST"),
+		.WRITE_MODE_B("READ_FIRST")
 	) _TECHMAP_REPLACE_ (
 		.DOBDO(DO[31:16]),
 		.DOADO(DO[15:0]),
@@ -204,8 +204,8 @@ module \$__XILINX_RAMB18_TDP18 (CLK2, CLK3, A1ADDR, A1DATA, B1ADDR, B1DATA, B1EN
 		.READ_WIDTH_B(18),
 		.WRITE_WIDTH_A(18),
 		.WRITE_WIDTH_B(18),
-		.WRITE_MODE_A(TRANSP2 ? "WRITE_FIRST" : "READ_FIRST"),
-		.WRITE_MODE_B(TRANSP2 ? "WRITE_FIRST" : "READ_FIRST")
+		.WRITE_MODE_A("READ_FIRST"),
+		.WRITE_MODE_B("READ_FIRST")
 	) _TECHMAP_REPLACE_ (
 		.DIADI(16'b0),
 		.DIPADIP(2'b0),
@@ -277,8 +277,8 @@ module \$__XILINX_RAMB18_TDP9 (CLK2, CLK3, A1ADDR, A1DATA, B1ADDR, B1DATA, B1EN)
 		.READ_WIDTH_B(9),
 		.WRITE_WIDTH_A(9),
 		.WRITE_WIDTH_B(9),
-		.WRITE_MODE_A(TRANSP2 ? "WRITE_FIRST" : "READ_FIRST"),
-		.WRITE_MODE_B(TRANSP2 ? "WRITE_FIRST" : "READ_FIRST")
+		.WRITE_MODE_A("READ_FIRST"),
+		.WRITE_MODE_B("READ_FIRST")
 	) _TECHMAP_REPLACE_ (
 		.DIADI(16'b0),
 		.DIPADIP(2'b0),
@@ -350,8 +350,8 @@ module \$__XILINX_RAMB18_TDP4 (CLK2, CLK3, A1ADDR, A1DATA, B1ADDR, B1DATA, B1EN)
 		.READ_WIDTH_B(4),
 		.WRITE_WIDTH_A(4),
 		.WRITE_WIDTH_B(4),
-		.WRITE_MODE_A(TRANSP2 ? "WRITE_FIRST" : "READ_FIRST"),
-		.WRITE_MODE_B(TRANSP2 ? "WRITE_FIRST" : "READ_FIRST")
+		.WRITE_MODE_A("READ_FIRST"),
+		.WRITE_MODE_B("READ_FIRST")
 	) _TECHMAP_REPLACE_ (
 		.DIADI(16'b0),
 		.DIPADIP(2'b0),
@@ -423,8 +423,8 @@ module \$__XILINX_RAMB18_TDP2 (CLK2, CLK3, A1ADDR, A1DATA, B1ADDR, B1DATA, B1EN)
 		.READ_WIDTH_B(2),
 		.WRITE_WIDTH_A(2),
 		.WRITE_WIDTH_B(2),
-		.WRITE_MODE_A(TRANSP2 ? "WRITE_FIRST" : "READ_FIRST"),
-		.WRITE_MODE_B(TRANSP2 ? "WRITE_FIRST" : "READ_FIRST")
+		.WRITE_MODE_A("READ_FIRST"),
+		.WRITE_MODE_B("READ_FIRST")
 	) _TECHMAP_REPLACE_ (
 		.DIADI(16'b0),
 		.DIPADIP(2'b0),
@@ -496,8 +496,8 @@ module \$__XILINX_RAMB18_TDP1 (CLK2, CLK3, A1ADDR, A1DATA, B1ADDR, B1DATA, B1EN)
 		.READ_WIDTH_B(1),
 		.WRITE_WIDTH_A(1),
 		.WRITE_WIDTH_B(1),
-		.WRITE_MODE_A(TRANSP2 ? "WRITE_FIRST" : "READ_FIRST"),
-		.WRITE_MODE_B(TRANSP2 ? "WRITE_FIRST" : "READ_FIRST")
+		.WRITE_MODE_A("READ_FIRST"),
+		.WRITE_MODE_B("READ_FIRST")
 	) _TECHMAP_REPLACE_ (
 		.DIADI(16'b0),
 		.DIPADIP(2'b0),