From: lkcl <lkcl@web>
Date: Wed, 4 May 2022 11:27:02 +0000 (+0100)
Subject: (no commit message)
X-Git-Tag: opf_rfc_ls005_v1~2481
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=d1ebe8b9d51ccc30d0caa4007e49fd08871bd626;p=libreriscv.git

---

diff --git a/openpower/sv/bitmanip.mdwn b/openpower/sv/bitmanip.mdwn
index 0a2b37c75..8322aa8d7 100644
--- a/openpower/sv/bitmanip.mdwn
+++ b/openpower/sv/bitmanip.mdwn
@@ -253,6 +253,23 @@ uint_xlen_t intabs(uint_xlen_t rs1, uint_xlen_t rs2) {
 }
 ```
 
+# shift-and-add
+
+Power ISA is missing LD/ST with shift, which is present in both ARM and x86.
+Too complex to add more LD/ST, a compromise is to add shift-and-add.
+Replaces a pair of explicit instructions in hot-loops.
+
+```
+uint_xlen_t shadd(uint_xlen_t rs1, uint_xlen_t rs2, uint8_t sh) {
+    return (rs1 << sh) + rs2;
+}
+
+uint_xlen_t shadduw(uint_xlen_t rs1, uint_xlen_t rs2, uint8_t sh) {
+    uint_xlen_t rs1z = rs1 & 0xFFFFFFFF;
+    return (rs1z << sh) + rs2;
+}
+```
+
 # cmix
 
 based on RV bitmanip, covered by ternlog bitops