From: Marek Olšák <marek.olsak@amd.com>
Date: Thu, 23 Nov 2017 23:19:56 +0000 (+0100)
Subject: radeonsi: clear PIPE_IMAGE_ACCESS_WRITE when it's invalid to be on the safe side
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=d1f65e5e99cf4e8384dce2dd1602248fd459e15b;p=mesa.git

radeonsi: clear PIPE_IMAGE_ACCESS_WRITE when it's invalid to be on the safe side

Tested-by: Dieter Nützel <Dieter@nuetzel-hh.de>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
---

diff --git a/src/gallium/drivers/radeonsi/si_descriptors.c b/src/gallium/drivers/radeonsi/si_descriptors.c
index 69371ea8910..5fbca541952 100644
--- a/src/gallium/drivers/radeonsi/si_descriptors.c
+++ b/src/gallium/drivers/radeonsi/si_descriptors.c
@@ -688,6 +688,16 @@ static void si_set_shader_image_desc(struct si_context *ctx,
 		unsigned level = view->u.tex.level;
 		unsigned width, height, depth, hw_level;
 		bool uses_dcc = vi_dcc_enabled(tex, level);
+		unsigned access = view->access;
+
+		/* Clear the write flag when writes can't occur.
+		 * Note that DCC_DECOMPRESS for MSAA doesn't work in some cases,
+		 * so we don't wanna trigger it.
+		 */
+		if (tex->is_depth || tex->resource.b.b.nr_samples >= 2) {
+			assert(!"Z/S and MSAA image stores are not supported");
+			access &= ~PIPE_IMAGE_ACCESS_WRITE;
+		}
 
 		assert(!tex->is_depth);
 		assert(tex->fmask.size == 0);