From: bugzilla-daemon <bugzilla-daemon@libre-soc.org>
Date: Sat, 6 Jun 2020 20:33:53 +0000 (+0000)
Subject: [libre-riscv-dev] [Bug 336] ALU CompUnit needs to recognise that RA (src1) can be... 
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=d200b30b1f6b0baf3753adfaeaad6d3f40bac58a;p=libre-riscv-dev.git

[libre-riscv-dev] [Bug 336] ALU CompUnit needs to recognise that RA (src1) can be zero
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+Date: Sat, 06 Jun 2020 20:33:53 +0000
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+X-Bugzilla-Severity: enhancement
+X-Bugzilla-Who: cestrauss@gmail.com
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+Message-ID: <bug-336-13-rdgkKa0ZXL@https.bugs.libre-soc.org/>
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+Subject: [libre-riscv-dev] [Bug 336] ALU CompUnit needs to recognise that RA
+ (src1) can be zero
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