From: Clifford Wolf <clifford@clifford.at>
Date: Tue, 2 Jul 2019 09:36:26 +0000 (+0200)
Subject: Fix read_verilog assert/assume/etc on default case label, fixes YosysHQ/SymbiYosys#53
X-Git-Tag: working-ls180~1229
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=d206eca03b8aa7bb982fb2486c02c90a61354066;p=yosys.git

Fix read_verilog assert/assume/etc on default case label, fixes YosysHQ/SymbiYosys#53

Signed-off-by: Clifford Wolf <clifford@clifford.at>
---

diff --git a/frontends/verilog/verilog_lexer.l b/frontends/verilog/verilog_lexer.l
index d3fd91473..951d9c66f 100644
--- a/frontends/verilog/verilog_lexer.l
+++ b/frontends/verilog/verilog_lexer.l
@@ -193,6 +193,8 @@ YOSYS_NAMESPACE_END
     to fix parsing of cells otherwise. (the current cell parser forces a reduce very early to update some
     global state.. its a mess) */
 [a-zA-Z_$][a-zA-Z0-9_$]*/[ \t\r\n]*:[ \t\r\n]*(assert|assume|cover|restrict)[^a-zA-Z0-9_$\.] {
+	if (!strcmp(yytext, "default"))
+		return TOK_DEFAULT;
 	frontend_verilog_yylval.string = new std::string(std::string("\\") + yytext);
 	return TOK_SVA_LABEL;
 }