From: Chris Wilson <chris@chris-wilson.co.uk>
Date: Tue, 31 Jul 2018 13:47:02 +0000 (+0100)
Subject: iris: AMD_pinned_memory
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=d209cc51709c2511b7d063388ef79689958bb65b;p=mesa.git

iris: AMD_pinned_memory

(rebased by Ken, mainly set res->internal_format)
---

diff --git a/src/gallium/drivers/iris/iris_resource.c b/src/gallium/drivers/iris/iris_resource.c
index 5061c452e23..9eb5816d772 100644
--- a/src/gallium/drivers/iris/iris_resource.c
+++ b/src/gallium/drivers/iris/iris_resource.c
@@ -362,6 +362,49 @@ tiling_to_modifier(uint32_t tiling)
    return map[tiling];
 }
 
+static struct pipe_resource *
+iris_resource_from_user_memory(struct pipe_screen *pscreen,
+                               const struct pipe_resource *templ,
+                               void *user_memory)
+{
+   struct iris_screen *screen = (struct iris_screen *)pscreen;
+   struct iris_bufmgr *bufmgr = screen->bufmgr;
+   struct iris_resource *res = iris_alloc_resource(pscreen, templ);
+   if (!res)
+      return NULL;
+
+   res->bo = iris_bo_create_userptr(bufmgr, "user",
+                                    user_memory, templ->width0,
+                                    IRIS_MEMZONE_OTHER);
+   if (!res->bo) {
+      free(res);
+      return NULL;
+   }
+
+   res->internal_format = templ->format;
+
+   // XXX: usage...
+   isl_surf_usage_flags_t isl_usage = 0;
+
+   isl_surf_init(&screen->isl_dev, &res->surf,
+                 .dim = target_to_isl_surf_dim(templ->target),
+                 .format = iris_isl_format_for_pipe_format(templ->format),
+                 .width = templ->width0,
+                 .height = templ->height0,
+                 .depth = templ->depth0,
+                 .levels = templ->last_level + 1,
+                 .array_len = templ->array_size,
+                 .samples = MAX2(templ->nr_samples, 1),
+                 .min_alignment_B = 0,
+                 .row_pitch_B = 0,
+                 .usage = isl_usage,
+                 .tiling_flags = 1 << ISL_TILING_LINEAR);
+
+   assert(res->bo->tiling_mode == isl_tiling_to_i915_tiling(res->surf.tiling));
+
+   return &res->base;
+}
+
 static struct pipe_resource *
 iris_resource_from_handle(struct pipe_screen *pscreen,
                           const struct pipe_resource *templ,
@@ -850,6 +893,7 @@ iris_init_screen_resource_functions(struct pipe_screen *pscreen)
    pscreen->resource_create_with_modifiers =
       iris_resource_create_with_modifiers;
    pscreen->resource_create = u_transfer_helper_resource_create;
+   pscreen->resource_from_user_memory = iris_resource_from_user_memory;
    pscreen->resource_from_handle = iris_resource_from_handle;
    pscreen->resource_get_handle = iris_resource_get_handle;
    pscreen->resource_destroy = u_transfer_helper_resource_destroy;
diff --git a/src/gallium/drivers/iris/iris_screen.c b/src/gallium/drivers/iris/iris_screen.c
index 7a179f9aaeb..850cbfbcf78 100644
--- a/src/gallium/drivers/iris/iris_screen.c
+++ b/src/gallium/drivers/iris/iris_screen.c
@@ -89,6 +89,7 @@ static int
 iris_get_param(struct pipe_screen *pscreen, enum pipe_cap param)
 {
    struct iris_screen *screen = (struct iris_screen *)pscreen;
+   const struct gen_device_info *devinfo = &screen->devinfo;
 
    switch (param) {
    case PIPE_CAP_NPOT_TEXTURES:
@@ -283,6 +284,14 @@ iris_get_param(struct pipe_screen *pscreen, enum pipe_cap param)
    case PIPE_CAP_FRAMEBUFFER_MSAA_CONSTRAINTS:
       return 0;
    case PIPE_CAP_RESOURCE_FROM_USER_MEMORY:
+      /* AMD_pinned_memory assumes the flexibility of using client memory
+       * for any buffer (incl. vertex buffers) which rules out the prospect
+       * of using snooped buffers, as using snooped buffers without
+       * cogniscience is likely to be detrimental to performance and require
+       * extensive checking in the driver for correctness, e.g. to prevent
+       * illegal snoop <-> snoop transfers.
+       */
+      return devinfo->has_llc;
    case PIPE_CAP_DEVICE_RESET_STATUS_QUERY:
    case PIPE_CAP_TGSI_TXQS:
    case PIPE_CAP_SHAREABLE_SHADERS: