From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Sat, 17 Nov 2018 06:58:14 +0000 (+0000)
Subject: c_lwsp fix-up to use src_pred, and pass width not xlen into READ_REG bitwidth
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=d20e46b75ab1331dfeab17b48ca1489dc68a56c8;p=riscv-isa-sim.git

c_lwsp fix-up to use src_pred, and pass width not xlen into READ_REG bitwidth
---

diff --git a/id_regs.py b/id_regs.py
index 804010d..c641c90 100644
--- a/id_regs.py
+++ b/id_regs.py
@@ -166,6 +166,7 @@ def find_registers(fname, insn, twin_predication, immed_offset, is_branch):
     predargs = ['dest_pred'] * 5
     if immed_offset: # C.LWSP
         if immed_offset == 'LD':
+            predargs[4] = 'src_pred'
             predargs.append('&src_pred')
         else:
             predargs.append('&dest_pred')
diff --git a/riscv/insns/c_lwsp.h b/riscv/insns/c_lwsp.h
index e0bf8cb..0be53a9 100644
--- a/riscv/insns/c_lwsp.h
+++ b/riscv/insns/c_lwsp.h
@@ -1,3 +1,3 @@
 require_extension('C');
 require(insn.insn_t::rvc_rd() != 0);
-WRITE_RD(MMU.load_int32(insn.rvc_sp(false), insn.rvc_lwsp_imm()));
+WRITE_RD(MMU.load_int32(insn.rvc_sp(), insn.rvc_lwsp_imm()));
diff --git a/riscv/sv_insn_redirect.cc b/riscv/sv_insn_redirect.cc
index 5744f03..ce48de7 100644
--- a/riscv/sv_insn_redirect.cc
+++ b/riscv/sv_insn_redirect.cc
@@ -317,7 +317,7 @@ reg_t sv_proc_t::READ_REG(reg_spec_t const& spec,
                          bool addr_mode, size_t width)
 {
     reg_t reg = spec.reg;
-    int bitwidth = get_bitwidth(_insn->reg_elwidth(reg, true), xlen);
+    int bitwidth = get_bitwidth(_insn->reg_elwidth(reg, true), width);
     int shift = 0;
     int origoffs = 0;
     int offs = 0;
@@ -1205,19 +1205,15 @@ sv_reg_t sv_proc_t::mmu_load(reg_spec_t const& spec, sv_reg_t const& offs,
     // addr_mode doesn't truncate the register to elwidth-specified
     // bitsize, it adds a modulo-offset based on the current VL loop index
     reg_t reg = READ_REG(spec, true, width);
-    uint64_t regoffs = 0;
-    //if (spec.offset && !spec.isvec) {
-    //    regoffs = *spec.offset;
-    //}
-    sv_reg_t addr = sv_reg_t((uint64_t)reg + (uint64_t)regoffs + (int64_t)offs);
+    sv_reg_t addr = sv_reg_t((uint64_t)reg + (int64_t)offs);
     sv_reg_t v(0);
 
     // now that the address has been moved on by the modulo-offset,
     // get only an elwidth-sized element (if not "default")
     uint8_t rwidth = _insn->reg_elwidth(spec.reg, true);
     width = get_bitwidth(rwidth, width);
-    fprintf(stderr, "mmu_load wid %ld reg %lx regoffs %lx offs %lx\n",
-                    width, (uint64_t)reg, regoffs, (int64_t)offs);
+    fprintf(stderr, "mmu_load wid %ld reg %lx offs %lx\n",
+                    width, (uint64_t)reg, (int64_t)offs);
     switch (width)
     {
         case 8: