From: Kyrylo Tkachov Date: Tue, 17 May 2016 12:15:05 +0000 (+0000) Subject: [AArch64] PR target/70809: Delete aarch64_vmls pattern X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=d20faa6624d6871e7c8c909fe6b9b5be0d4cae9b;p=gcc.git [AArch64] PR target/70809: Delete aarch64_vmls pattern PR target/70809 * config/aarch64/aarch64-simd.md (aarch64_vmls): Delete. * gcc.target/aarch64/pr70809_1.c: New test. From-SVN: r236318 --- diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 0d3e00f42b9..3c6030d427a 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,8 @@ +2016-05-17 Kyrylo Tkachov + + PR target/70809 + * config/aarch64/aarch64-simd.md (aarch64_vmls): Delete. + 2016-05-17 James Greenhalgh * config/aarch64/aarch64-elf.h (ASM_OUTPUT_DEF): Delete. diff --git a/gcc/config/aarch64/aarch64-simd.md b/gcc/config/aarch64/aarch64-simd.md index bd73bce6441..ded8bff0973 100644 --- a/gcc/config/aarch64/aarch64-simd.md +++ b/gcc/config/aarch64/aarch64-simd.md @@ -1919,16 +1919,6 @@ } ) -(define_insn "aarch64_vmls" - [(set (match_operand:VDQF 0 "register_operand" "=w") - (minus:VDQF (match_operand:VDQF 1 "register_operand" "0") - (mult:VDQF (match_operand:VDQF 2 "register_operand" "w") - (match_operand:VDQF 3 "register_operand" "w"))))] - "TARGET_SIMD" - "fmls\\t%0., %2., %3." - [(set_attr "type" "neon_fp_mla__scalar")] -) - ;; FP Max/Min ;; Max/Min are introduced by idiom recognition by GCC's mid-end. An ;; expression like: diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog index 1f8a5a60a78..9f75baa32a5 100644 --- a/gcc/testsuite/ChangeLog +++ b/gcc/testsuite/ChangeLog @@ -1,3 +1,8 @@ +2016-05-17 Kyrylo Tkachov + + PR target/70809 + * gcc.target/aarch64/pr70809_1.c: New test. + 2016-05-17 Kyrylo Tkachov * gcc.target/aarch64/cpu-diagnostics-1.c: Skip if -mcpu is overriden. diff --git a/gcc/testsuite/gcc.target/aarch64/pr70809_1.c b/gcc/testsuite/gcc.target/aarch64/pr70809_1.c new file mode 100644 index 00000000000..df88c71c42a --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/pr70809_1.c @@ -0,0 +1,18 @@ +/* PR target/70809. */ +/* { dg-do compile } */ +/* { dg-options "-O2 -ftree-vectorize -ffp-contract=off -mtune=xgene1" } */ + +/* Check that vector FMLS is not generated when contraction is disabled. */ + +void +foo (float *__restrict__ __attribute__ ((aligned (16))) a, + float *__restrict__ __attribute__ ((aligned (16))) x, + float *__restrict__ __attribute__ ((aligned (16))) y, + float *__restrict__ __attribute__ ((aligned (16))) z) +{ + unsigned i = 0; + for (i = 0; i < 256; i++) + a[i] = x[i] - (y[i] * z[i]); +} + +/* { dg-final { scan-assembler-not "fmls\tv.*" } } */