From: lkcl <lkcl@web>
Date: Wed, 30 Dec 2020 15:26:36 +0000 (+0000)
Subject: (no commit message)
X-Git-Tag: convert-csv-opcode-to-binary~726
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=d210e4e086c7c1317603d32b687fb890dee655c2;p=libreriscv.git

---

diff --git a/openpower/sv/svp64.mdwn b/openpower/sv/svp64.mdwn
index c590420c6..9f6b7cb1b 100644
--- a/openpower/sv/svp64.mdwn
+++ b/openpower/sv/svp64.mdwn
@@ -153,20 +153,7 @@ Following the prefix will be the suffix: this is simply a 32-bit v3.0B / v3.1B
 instruction.  That instruction becomes "prefixed" with the SVP context: the
 Remapped Encoding field (RM).
 
-# Remapped Encoding Fields
-
-Shows all fields in the Remapped Encoding `RM[0:23]` for all instruction
-variants.  There are two categories:  Single and Twin Predication.
-Due to space considerations further subdivision of Single Predication
-is based on whether the number of src operands is 2 or 3.
-
-* `RM-1P-3S1D` Single Predication dest/src1/2/3, applies to 4-operand instructions (fmadd, isel, madd).
-* `RM-1P-2S1D` Single Predication dest/src1/2 applies to 3-operand instructions (src1 src2 dest)
-* `RM-2P-1S1D` Twin Predication (src=1, dest=1)
-* `RM-2P-2S1D` Twin Predication (src=2, dest=1) primarily for LDST (Indexed)
-* `RM-2P-1S2D` Twin Predication (src=1, dest=2) primarily for LDST Update
-
-## Common RM fields
+# Common RM fields
 
 The following fields are common to all Remapped Encodings:
 
@@ -181,6 +168,19 @@ The following fields are common to all Remapped Encodings:
 
 Bits 9 to 18 are further decoded depending on RM category for the instruction.
 
+# Extra Remapped Encoding
+
+Shows all fields in the Remapped Encoding `RM[0:23]` for all instruction
+variants.  There are two categories:  Single and Twin Predication.
+Due to space considerations further subdivision of Single Predication
+is based on whether the number of src operands is 2 or 3.  The full list of which instructions use which remaps is here [[opcode_regs_deduped]].
+
+* `RM-1P-3S1D` Single Predication dest/src1/2/3, applies to 4-operand instructions (fmadd, isel, madd).
+* `RM-1P-2S1D` Single Predication dest/src1/2 applies to 3-operand instructions (src1 src2 dest)
+* `RM-2P-1S1D` Twin Predication (src=1, dest=1)
+* `RM-2P-2S1D` Twin Predication (src=2, dest=1) primarily for LDST (Indexed)
+* `RM-2P-1S2D` Twin Predication (src=1, dest=2) primarily for LDST Update
+
 ## RM-1P-3S1D
 
 | Field Name | Field bits | Description                            |