From: Ali Saidi <saidi@eecs.umich.edu>
Date: Thu, 3 Jun 2010 16:20:49 +0000 (-0400)
Subject: ARM: Fix issue with m5.fast and ARM
X-Git-Tag: stable_2012_02_02~1051
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=d2186857b15ccdfe58b6d9e1369946253c28fb02;p=gem5.git

ARM: Fix issue with m5.fast and ARM
---

diff --git a/src/arch/arm/isa.cc b/src/arch/arm/isa.cc
index 60f00e438..17f95e57d 100644
--- a/src/arch/arm/isa.cc
+++ b/src/arch/arm/isa.cc
@@ -424,10 +424,7 @@ ISA::setMiscReg(int misc_reg, const MiscReg &val, ThreadContext *tc)
                       flags = TLB::MustBeOne | TLB::UserMode;
                       mode = BaseTLB::Write;
                       break;
-                  case MISCREG_V2POWPR:
-                  case MISCREG_V2POWPW:
-                  case MISCREG_V2POWUR:
-                  case MISCREG_V2POWUW:
+                  default:
                       panic("Security Extensions not implemented!");
               }
               req->setVirt(0, val, 1, flags, tc->readPC());