From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Mon, 15 Jun 2020 23:52:30 +0000 (+0100)
Subject: start trying to fill in some comments in Minerva L1 cache code
X-Git-Tag: div_pipeline~367
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=d2202b1c36f6a4eccfdfab4ea598e877097cb2cb;p=soc.git

start trying to fill in some comments in Minerva L1 cache code
---

diff --git a/src/soc/minerva/cache.py b/src/soc/minerva/cache.py
index dabcb3a7..bfa25f6b 100644
--- a/src/soc/minerva/cache.py
+++ b/src/soc/minerva/cache.py
@@ -29,23 +29,26 @@ class L1Cache(Elaboratable):
         linebits = log2_int(nlines)
         tagbits = log2_int(limit-base) - log2_int(nlines) - log2_int(nwords) - 2
 
+        # stage 1: address checking (is it in the cache?)
         self.s1_addr = Record([("offset", offsetbits),
                                ("line", linebits),
                                ("tag", tagbits)])
         self.s1_flush = Signal()
         self.s1_stall = Signal()
         self.s1_valid = Signal()
+
+        # stage 2: if not, what now? (XXX: what is it?? no explanation, at all)
         self.s2_addr = Record.like(self.s1_addr)
-        self.s2_re = Signal()
+        self.s2_re = Signal()       # read-enable?
         self.s2_evict = Signal()
         self.s2_valid = Signal()
         self.bus_valid = Signal()
         self.bus_error = Signal()
-        self.bus_rdata = Signal(32)
+        self.bus_rdata = Signal(32) # read data?
 
         self.s2_miss = Signal()
-        self.s2_rdata = Signal(32)
-        self.bus_re = Signal()
+        self.s2_rdata = Signal(32) # write data?
+        self.bus_re = Signal()     # read-enable?
         self.bus_addr = Record.like(self.s1_addr)
         self.bus_last = Signal()