From: lkcl <lkcl@web>
Date: Wed, 30 Dec 2020 17:12:16 +0000 (+0000)
Subject: (no commit message)
X-Git-Tag: convert-csv-opcode-to-binary~703
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=d2283f483a843a9cb0c2922795a178b410603add;p=libreriscv.git

---

diff --git a/openpower/sv/overview.mdwn b/openpower/sv/overview.mdwn
index 83562d986..5dec88c8f 100644
--- a/openpower/sv/overview.mdwn
+++ b/openpower/sv/overview.mdwn
@@ -76,8 +76,10 @@ basis further refinements can be added which build up towards an extremely
 powerful Vector augmentation system, with very little in the way of
 additional opcodes required: simply external "context".
 
-RISC-V RVV as of version 0.9 is over 180 instructions (more than the
-rest of RV64G combined). Over 95% of that functionality is added to
+x86 was originally only 70 instructions: prior to AVX512 1,400 additional ibsteuctions have been added, almost all of them related to SIMD.
+
+RISC-V RVV as of version 0.9 is over 188 instructions (more than the
+rest of RV64G combined: 80 for RV64G and 27 for C). Over 95% of that functionality is added to
 OpenPOWER v3 0B, by SimpleV augmentation, with around 5 to 8 instructions.
 
 Even in OpenPOWER v3.0B, the Scalar Integer ISA is around 150