From: lkcl <lkcl@web>
Date: Wed, 29 Mar 2023 21:52:39 +0000 (+0100)
Subject: (no commit message)
X-Git-Tag: opf_rfc_ls012_v1~223
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=d230320629782f81788576d6de6d7068bab807e2;p=libreriscv.git

---

diff --git a/openpower/sv/rfc/ls010.mdwn b/openpower/sv/rfc/ls010.mdwn
index d43fbb1ea..7c72f5571 100644
--- a/openpower/sv/rfc/ls010.mdwn
+++ b/openpower/sv/rfc/ls010.mdwn
@@ -231,7 +231,7 @@ be confused with MAXVL when understanding this key aspect of SimpleV.
 
 ## Register Naming and size
 
-As indicated above SV Registers are simply the INT, FP and CR
+As indicated above SV Registers are simply the GPR, FPR and CR
 register files extended linearly to larger sizes; SV Vectorisation
 iterates sequentially through these registers (LSB0 sequential ordering
 from 0 to VL-1).