From: Sebastien Bourdeauducq <sebastien@milkymist.org>
Date: Fri, 1 Mar 2013 11:06:12 +0000 (+0100)
Subject: csr/SRAM: prefix page register with memory name
X-Git-Tag: 24jan2021_ls180~2099^2~680
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=d2491828a426f8167709e543969777549e1b72a8;p=litex.git

csr/SRAM: prefix page register with memory name
---

diff --git a/migen/bus/csr.py b/migen/bus/csr.py
index 264c63c0..9deb334b 100644
--- a/migen/bus/csr.py
+++ b/migen/bus/csr.py
@@ -62,7 +62,7 @@ class SRAM:
 		self.address = address
 		page_bits = _compute_page_bits(self.mem.depth)
 		if page_bits:
-			self._page = RegisterField("page", page_bits)
+			self._page = RegisterField(self.mem.name_override + "_page", page_bits)
 		else:
 			self._page = None
 		if bus is None: