From: Eddie Hung <eddie@fpgeh.com>
Date: Tue, 16 Apr 2019 18:21:46 +0000 (-0700)
Subject: synth_xilinx: before abc read +/xilinx/cells_box.v
X-Git-Tag: working-ls180~1208^2~341
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=d259e6dc14dadf9101116c622569f5b961adde69;p=yosys.git

synth_xilinx: before abc read +/xilinx/cells_box.v
---

diff --git a/techlibs/xilinx/synth_xilinx.cc b/techlibs/xilinx/synth_xilinx.cc
index 0058f626f..c10e42532 100644
--- a/techlibs/xilinx/synth_xilinx.cc
+++ b/techlibs/xilinx/synth_xilinx.cc
@@ -283,6 +283,7 @@ struct SynthXilinxPass : public Pass
 		{
 			Pass::call(design, "opt -full");
 			Pass::call(design, "techmap -map +/techmap.v");
+			Pass::call(design, "read_verilog +/xilinx/cells_box.v");
 			if (abc == "abc9")
 				Pass::call(design, abc + " -lut +/xilinx/cells.lut -box +/xilinx/cells.box" + string(retime ? " -dff" : ""));
 			else