From: Eddie Hung <eddie@fpgeh.com>
Date: Fri, 16 Aug 2019 23:07:29 +0000 (-0700)
Subject: Add doc for abc_* attributes
X-Git-Tag: working-ls180~1123^2~4
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=d26c512d7ef5369f26436540efee40201e480f7f;p=yosys.git

Add doc for abc_* attributes
---

diff --git a/README.md b/README.md
index d9989eb29..5b30f6bae 100644
--- a/README.md
+++ b/README.md
@@ -405,6 +405,22 @@ Verilog Attributes and non-standard features
   blackboxes and whiteboxes. Use ``read_verilog -specify`` to enable this
   functionality. (By default specify .. endspecify blocks are ignored.)
 
+- The module attribute ``abc_box_id`` specifies a positive integer linking a
+  blackbox or whitebox definition to a corresponding entry in a `abc9`
+  box-file.
+
+- The port attribute ``abc_scc_break`` indicates a module input port that will
+  be treated as a primary output during `abc9` techmapping. Doing so eliminates
+  the possibility of a strongly-connected component (i.e. a combinatorial loop)
+  existing. Typically, this is specified for sequential inputs on otherwise
+  combinatorial boxes -- for example, applying ``abc_scc_break`` onto the `D`
+  port of a LUTRAM cell prevents `abc9` from interpreting any `Q` -> `D` paths
+  as a combinatorial loop.
+
+- The port attribute ``abc_carry_in`` and ``abc_carry_out`` attributes mark
+  the carry-in and carry-out ports of a box. This information is necessary for
+  `abc9` to preserve the integrity of carry-chains.
+
 
 Non-standard or SystemVerilog features for formal verification
 ==============================================================