From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Mon, 16 Apr 2018 08:03:05 +0000 (+0100)
Subject: add SIMD comparison section
X-Git-Tag: convert-csv-opcode-to-binary~5656
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=d2792f2392c890afaf2eeebedee8c9c0f50f2460;p=libreriscv.git

add SIMD comparison section
---

diff --git a/simple_v_extension.mdwn b/simple_v_extension.mdwn
index 0ee3985ba..6788ed789 100644
--- a/simple_v_extension.mdwn
+++ b/simple_v_extension.mdwn
@@ -1171,8 +1171,9 @@ get good performance.  Unfortunately that makes it quite seductive...
 * minus: EVEN BIGGER proliferation of SIMD ISA if the functionality of
   8, 16, 32 or 64-bit reordering is built-in to the SIMD instruction.
   For example: add (high|low) 16-bits of r1 to (low|high) of r2 requires
-  two separate and distinct instructions: one for (r1:low r2:high) and
-  one for (r1:high r2:low) *per function*.
+  four separate and distinct instructions: one for (r1:low r2:high),
+  one for (r1:high r2:low), one for (r1:high r2:high) and one for
+  (r1:low r2:low) *per function*.
 * minus: EVEN BIGGER proliferation of SIMD ISA if there is a mismatch
   between operand and result bit-widths.  In combination with high/low
   proliferation the situation is made even worse.