From: Sebastien Bourdeauducq <sebastien@milkymist.org>
Date: Fri, 8 Jun 2012 12:00:49 +0000 (+0200)
Subject: examples/fir: print Verilog source
X-Git-Tag: 24jan2021_ls180~2099^2~939
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=d280723618b8a75c7f6a0d283c89b0fc43410af4;p=litex.git

examples/fir: print Verilog source
---

diff --git a/examples/fir.py b/examples/fir.py
index e10ff94e..2119679f 100644
--- a/examples/fir.py
+++ b/examples/fir.py
@@ -76,5 +76,9 @@ def main():
 	plt.plot(in_signals)
 	plt.plot(out_signals)
 	plt.show()
+	
+	# Print the Verilog source for the filter.
+	print(verilog.convert(fir.get_fragment(),
+		ios={fir.i, fir.o}))
 
 main()