From: David Shah <dave@ds0.me>
Date: Thu, 18 Oct 2018 18:40:02 +0000 (+0100)
Subject: ecp5: Sim model fixes
X-Git-Tag: yosys-0.9~435^2
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=d29b517fef05973dda3c556a95fbfb478d6e7e50;p=yosys.git

ecp5: Sim model fixes

Signed-off-by: David Shah <dave@ds0.me>
---

diff --git a/techlibs/ecp5/cells_sim.v b/techlibs/ecp5/cells_sim.v
index e43632c64..6e4b0a5ac 100644
--- a/techlibs/ecp5/cells_sim.v
+++ b/techlibs/ecp5/cells_sim.v
@@ -265,16 +265,18 @@ module TRELLIS_IO(
 	output O
 );
 	parameter DIR = "INPUT";
+	reg T_pd;
+	always @(*) if (T === 1'bz) T_pd <= 1'b0; else T_pd <= T;
 
 	generate
 		if (DIR == "INPUT") begin
 			assign B = 1'bz;
 			assign O = B;
 		end else if (DIR == "OUTPUT") begin
-			assign B = T ? 1'bz : I;
+			assign B = T_pd ? 1'bz : I;
 			assign O = 1'bx;
-		end else if (DIR == "INOUT") begin
-			assign B = T ? 1'bz : I;
+		end else if (DIR == "BIDIR") begin
+			assign B = T_pd ? 1'bz : I;
 			assign O = B;
 		end else begin
 			ERROR_UNKNOWN_IO_MODE error();