From: Alexandre Dumont aka Adlx <adumont@users.noreply.github.com>
Date: Sun, 28 Jun 2020 22:42:06 +0000 (+0200)
Subject: Tipo missing * in Global Clock example
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=d29f7b983736a516068823674e6733c84b3fa95c;p=SymbiYosys.git

Tipo missing * in Global Clock example
---

diff --git a/docs/source/verilog.rst b/docs/source/verilog.rst
index f43f71f..474514e 100644
--- a/docs/source/verilog.rst
+++ b/docs/source/verilog.rst
@@ -211,7 +211,7 @@ To use ``(* gclk *)``, define a register with that attribute, as in:
 
 .. code-block:: systemverilog
 
-    (* gclk ) reg formal_timestep;
+    (* gclk *) reg formal_timestep;
 
 You can then reference this ``formal_timestep`` in the clocking section
 of an always block, as in,