From: Luke Kenneth Casson Leighton Date: Wed, 15 May 2019 15:06:47 +0000 (+0100) Subject: make fn unit invert readable, however qualify with rd latch X-Git-Tag: div_pipeline~2043 X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=d2a49025a6ea8e578c870ac90b549ea4b812458c;p=soc.git make fn unit invert readable, however qualify with rd latch --- diff --git a/src/experiment/cscore.py b/src/experiment/cscore.py index 61f7ec09..707a0ea3 100644 --- a/src/experiment/cscore.py +++ b/src/experiment/cscore.py @@ -326,7 +326,7 @@ def scoreboard_sim(dut, alusim): #dest = 2 op = randint(0, 1) - op = i + op = 0 print ("random %d: %d %d %d %d\n" % (i, op, src1, src2, dest)) yield from int_instr(dut, alusim, op, src1, src2, dest) yield from print_reg(dut, [3,4,5]) diff --git a/src/scoreboard/fn_unit.py b/src/scoreboard/fn_unit.py index d706b7f1..3edabbde 100644 --- a/src/scoreboard/fn_unit.py +++ b/src/scoreboard/fn_unit.py @@ -163,9 +163,9 @@ class FnUnit(Elaboratable): # readable output signal g_rd = Signal(self.reg_width, reset_less=True) ro = Signal(reset_less=True) - m.d.comb += g_rd.eq(~self.g_wr_pend_i & self.rd_pend_o) - m.d.comb += ro.eq(g_rd.bool()) - m.d.comb += self.readable_o.eq(ro) + m.d.comb += g_rd.eq(self.g_wr_pend_i & self.rd_pend_o) + m.d.comb += ro.eq(~g_rd.bool()) + m.d.comb += self.readable_o.eq(ro & rd_l.q) # writable output signal g_wr_v = Signal(self.reg_width, reset_less=True)