From: Marek Olšák Date: Sun, 13 Nov 2016 16:30:54 +0000 (+0100) Subject: radeonsi: don't set vs.epilog.export_prim_id if TES is bound X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=d2a56985d7b4b22d176c13d8601f98e18e44d3a1;p=mesa.git radeonsi: don't set vs.epilog.export_prim_id if TES is bound there is no VS epilog in this case Tested-by: Edmondo Tommasina Reviewed-by: Nicolai Hähnle --- diff --git a/src/gallium/drivers/radeonsi/si_state_shaders.c b/src/gallium/drivers/radeonsi/si_state_shaders.c index 9df8f47e624..72d0518c6bd 100644 --- a/src/gallium/drivers/radeonsi/si_state_shaders.c +++ b/src/gallium/drivers/radeonsi/si_state_shaders.c @@ -881,10 +881,10 @@ static inline void si_shader_selector_key(struct pipe_context *ctx, key->as_ls = 1; else if (sctx->gs_shader.cso) key->as_es = 1; - - if (!sctx->gs_shader.cso && sctx->ps_shader.cso && - sctx->ps_shader.cso->info.uses_primid) - key->part.vs.epilog.export_prim_id = 1; + else { + if (sctx->ps_shader.cso && sctx->ps_shader.cso->info.uses_primid) + key->part.vs.epilog.export_prim_id = 1; + } break; case PIPE_SHADER_TESS_CTRL: key->part.tcs.epilog.prim_mode =