From: colepoirier@1ec9c8c87c85f09e4718cd80e0605065e33975f0 <colepoirier@1ec9c8c87c85f09e4718cd80e0605065e33975f0@web>
Date: Fri, 9 Apr 2021 20:48:03 +0000 (+0100)
Subject: (no commit message)
X-Git-Tag: DRAFT_SVP64_0_1~1077^2~17
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=d2a8eba72bb8b43a5d4676c8ed880742c0402087;p=libreriscv.git

---

diff --git a/HDL_workflow/ECP5_FPGA.mdwn b/HDL_workflow/ECP5_FPGA.mdwn
index fa61e6da1..ae8d70bd4 100644
--- a/HDL_workflow/ECP5_FPGA.mdwn
+++ b/HDL_workflow/ECP5_FPGA.mdwn
@@ -163,8 +163,9 @@ Board pin # (count) | Board pin label # | FPGA IO PAD | GPIO # (n/p) |   Label
 
 As noted in the schematic pins GP,GN 0-7 are single ended non-differential pairs, whereas pins GP,GN 8-13 I haven't mapped out here as they are bidirectional differential pairs.
 
+ft232 pin and wire colour table converted to jtag signal names:
 
-``` ft232 pin and wire colour table converted to jtag signal names
+```
  _________________________
 | Pin # | Name |  Colour  |
 |-------|------|----------|