From: Clifford Wolf Date: Fri, 3 May 2019 12:40:51 +0000 (+0200) Subject: Fix typo in tests/svinterfaces/runone.sh X-Git-Tag: yosys-0.9~159 X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=d2aa123226f39fb6d076b9a0add2ad4f0e596166;p=yosys.git Fix typo in tests/svinterfaces/runone.sh Signed-off-by: Clifford Wolf --- diff --git a/tests/svinterfaces/runone.sh b/tests/svinterfaces/runone.sh index 71c2d4976..54cf5f2ec 100755 --- a/tests/svinterfaces/runone.sh +++ b/tests/svinterfaces/runone.sh @@ -13,8 +13,8 @@ echo -n "Test: ${TESTNAME} -> " set -e -$PWD/../../yosys -p "read_verilog -sv ${TESTNAME}.sv ; hierarchy -check -top TopModule ; synth ; write_verilog ${TESTNAME}_syn.v" >> $STDOUTFILE >> $STDERRFILE -$PWD/../../yosys -p "read_verilog -sv ${TESTNAME}_ref.v ; hierarchy -check -top TopModule ; synth ; write_verilog ${TESTNAME}_ref_syn.v" >> $STDOUTFILE >> $STDERRFILE +$PWD/../../yosys -p "read_verilog -sv ${TESTNAME}.sv ; hierarchy -check -top TopModule ; synth ; write_verilog ${TESTNAME}_syn.v" >> $STDOUTFILE 2>> $STDERRFILE +$PWD/../../yosys -p "read_verilog -sv ${TESTNAME}_ref.v ; hierarchy -check -top TopModule ; synth ; write_verilog ${TESTNAME}_ref_syn.v" >> $STDOUTFILE 2>> $STDERRFILE rm -f a.out reference_result.txt dut_result.txt