From: Alec Roelke Date: Fri, 14 Jul 2017 22:09:06 +0000 (-0400) Subject: riscv: Define register index constants using literals X-Git-Tag: v19.0.0.0~2680 X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=d2ab7234685bd8c007d10a525f67265a1fcb5fa4;p=gem5.git riscv: Define register index constants using literals To make it clearer what the register indices are for the semantically meaningful registers defined by src/arch/riscv/registers.hh, the constants that were defined using other constants were changed to use the literal values of those constants. This also removes the need to use the M5_VAR_USED attribute. Change-Id: I7cccbe45d3d820deb5149a5925415735f6ae2e61 Reviewed-on: https://gem5-review.googlesource.com/4080 Reviewed-by: Gabe Black Maintainer: Alec Roelke --- diff --git a/src/arch/riscv/registers.hh b/src/arch/riscv/registers.hh index 114d7e9e1..01e385957 100644 --- a/src/arch/riscv/registers.hh +++ b/src/arch/riscv/registers.hh @@ -92,8 +92,8 @@ const int StackPointerReg = 2; const int GlobalPointerReg = 3; const int ThreadPointerReg = 4; const int FramePointerReg = 8; +const int ReturnValueReg = 10; const std::vector ReturnValueRegs = {10, 11}; -const int ReturnValueReg M5_VAR_USED = ReturnValueRegs[0]; const std::vector ArgumentRegs = {10, 11, 12, 13, 14, 15, 16, 17}; const int AMOTempReg = 32; @@ -118,10 +118,9 @@ const std::vector FloatRegNames = { "ft8", "ft9", "ft10", "ft11" }; -const int SyscallNumReg M5_VAR_USED = ArgumentRegs[7]; -const std::vector SyscallArgumentRegs = {ArgumentRegs[0], ArgumentRegs[1], - ArgumentRegs[2], ArgumentRegs[3]}; -const int SyscallPseudoReturnReg M5_VAR_USED = ReturnValueRegs[0]; +const int SyscallNumReg = 17; +const std::vector SyscallArgumentRegs = {10, 11, 12, 13}; +const int SyscallPseudoReturnReg = 10; enum MiscRegIndex { MISCREG_USTATUS = 0x000,